DRAM ECC Mask-Bit Update for Faster Data Access
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Solution Overview
Problem
In dynamic random access memory (DRAM), the existing error correction process requires a large chip area and long access time due to the need for an error correcting circuit, which complicates the write mask operation by first reading data, generating a new error correcting code, and updating it, thereby slowing down data access.
Innovation Solution
A memory storage apparatus and data access method that omit the error correction procedure for data input to a switch element, using a controller circuit with a bit confirmation circuit and error correcting code updater to determine if an error bit is a data mask bit, allowing for selective updating of error correcting codes without performing error correction on the data, thus simplifying the process and reducing access time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an error correcting circuit is equipped in the controller circuit to perform error correction on read data, then data reliability is improved, but chip area is increased and access time is extended
Solution Approach 1:
The patent extracts the error correction function from the controller circuit and implements it within the memory array itself. The memory array includes error correction units that can correct errors directly at the storage location, separating the error correction functionality from the controller circuit and reducing the controller's chip area requirements.
Solution Approach 2:
The memory array is segmented into multiple storage units, each with its own error correction unit. This segmentation allows error correction to be performed locally at each storage unit rather than requiring a centralized error correcting circuit in the controller, thereby reducing the controller's complexity and chip area.
2Reliability
If an error correcting circuit is equipped in the controller circuit to perform error correction on read data, then data reliability is improved, but access time is extended
Solution Approach 1:
The error correction units are pre-configured within each storage unit of the memory array, ready to perform error correction immediately when data is read. This preliminary preparation of correction capabilities eliminates the need for time-consuming error correction processing in the controller circuit after data retrieval.
Solution Approach 2:
By extracting the error correction function from the controller circuit and placing it within the memory array's storage units, the patent enables parallel error correction during the data read process itself, rather than requiring sequential error correction processing after data retrieval, thereby reducing access time.
3Reliability
If error correction is performed by reading data first and then generating new error correcting codes in the controller circuit, then data integrity is maintained, but the data access process becomes complex and slow
Solution Approach 1:
The memory array is divided into multiple independent storage units, each with its own error correction unit. This segmentation allows error correction to be performed independently at each storage unit during the write operation, eliminating the need for complex centralized error correction processing in the controller circuit.
Solution Approach 2:
Error correcting codes are generated and applied preliminary at each storage unit during the write operation itself, rather than requiring post-read error correction processing in the controller. This preliminary error correction preparation simplifies the data access process by maintaining data integrity at the storage level.
Data Source
AI summary
A memory storage apparatus including a memory array and a controller circuit is provided. The memory array is configured to store a first error correcting code and a first data. The controller circuit is coupled to the memory array. The controller circuit is configured to read the first data from the memory array and determine whether an error bit of the first data is one of one or more data mask bits to decide whether to update the first error correcting code stored in the memory array. The controller circuit includes a switch element. The switch element is coupled to the memory array. The switch element receives the first data from the memory array. An error correcting procedure is not performed on the first data. In addition, a data access method is also provided.