DRAM ECC Circuit Using Multi-Level Check Codes
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Solution Overview
Problem
Dynamic Random Access Memory (DRAM) systems face errors due to advanced manufacturing processes and higher storage density, which can significantly impact performance, necessitating effective error detection and correction mechanisms.
Innovation Solution
A storage system that generates multiple check codes (first, second, and third) to determine error states, allowing for efficient error detection and correction by identifying specific byte and bit errors using a combination of parity check codes and XOR/XNOR operations, reducing hardware complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ECC technology is applied to detect or correct errors in DRAM, then error detection and correction capability is improved, but hardware complexity and power consumption increase
Solution Approach 1:
The patent segments the error detection and correction process into multiple stages with different check code generation methods. The encoding circuit generates first check codes for individual bytes and second check codes for groups of bytes, allowing errors to be localized to specific regions before correction, thereby reducing the overall hardware complexity while maintaining comprehensive error coverage
Solution Approach 2:
The patent introduces a hierarchical dimension to error checking by organizing check codes at multiple levels: byte-level first check codes and group-level second check codes. This dimensional organization allows the system to efficiently locate errors by first identifying the affected byte group and then the specific byte within that group, reducing the search space and hardware requirements
2Reliability
If traditional ECC technology is applied to detect or correct errors in DRAM, then error detection and correction capability is improved, but power consumption increases
Solution Approach 1:
The patent segments the encoding process into multiple stages where check codes are generated progressively. By dividing the data into bytes and groups of bytes, the system processes smaller units separately, reducing the computational burden and power consumption at each stage while still providing comprehensive error coverage for the entire data set
Solution Approach 2:
The patent implements partial error checking by first generating check codes for individual bytes and then for groups of bytes. This staged approach allows the system to focus computational resources on locating errors in specific regions before applying correction, avoiding the need to process the entire data set uniformly and thereby reducing overall power consumption
3Measurement precision
If multiple check codes are generated to locate specific byte and bit errors, then error location precision is improved, but encoding and decoding time increases
Solution Approach 1:
The patent segments error location into a two-stage process: first, second check codes identify the affected byte group; second, first check codes identify the specific byte within that group. This segmentation narrows the search space at each stage, achieving precise error location while minimizing the total number of operations required compared to a single-stage comprehensive check
Solution Approach 2:
The patent performs preliminary error group identification using second check codes before conducting detailed byte-level analysis with first check codes. This preliminary action reduces the scope of subsequent detailed checking, allowing the system to quickly eliminate unaffected regions and focus computational resources only on potential error locations, thereby reducing overall encoding and decoding time
Data Source
AI summary
A storage system includes: a memory, configured to write or read a plurality of pieces of data during a read-write operation, the plurality of pieces of data being divided into M bytes, and each byte having N pieces of data; and an encoding circuit, configured to in the encoding stage, generate X first check codes based on the two or more pieces of data in each byte, generate Y second check codes based on all data of two or more bytes of the M bytes in the encoding stage, and generate a third check code based on the plurality of pieces of data, the X first check codes and the Y second check codes. The first check codes, the second check codes and the third check code are used to determine an error state of the plurality of pieces of data.