External DRAM ECC Page Layout Without Dedicated ECC Hardware
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Solution Overview
Problem
Conventional methods for error detection and correction in external DRAM chips for GPUs require additional I/O pins and DRAM chips, leading to unnecessary cost burdens for applications that do not need high computational integrity.
Innovation Solution
A method that initializes a write list data structure to manage ECC data within a DRAM page, allowing for ECC protection without additional DRAM components or I/O pins by integrating ECC data within the existing DRAM page, enabling transparent operation in both ECC and non-ECC modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC protection is implemented with additional I/O pins and DRAM chips, then error detection and correction capability is improved, but system cost and complexity increase significantly
Solution Approach 1:
The patent merges ECC data with application data into the same DRAM page, eliminating the need for separate ECC storage. The write list structure combines both data sectors and ECC sectors in a single data structure, allowing simultaneous management of both data types through unified write operations to the same memory page.
Solution Approach 2:
The patent makes existing DRAM pages serve dual purposes: storing both application data and ECC protection data. The same I/O pins and DRAM chips that store application data also store ECC data, making the memory system universally capable of both data storage and error correction without additional components.
2Reliability
If ECC protection is implemented with separate DRAM chips, then data integrity is improved, but memory capacity and cost increase
Solution Approach 1:
The patent combines ECC data and application data into the same DRAM page, utilizing existing memory capacity for dual purposes. This eliminates the need for additional DRAM chips dedicated to ECC storage, maintaining data integrity while preserving memory resources.
Solution Approach 2:
The patent changes the organizational parameters of DRAM pages by allocating specific sectors within each page for ECC data while maintaining the same physical memory structure. This reorganization allows existing memory capacity to provide both application storage and error correction without increasing quantity of memory substances.
3Reliability
If additional I/O pins are added for ECC transmission, then error protection is improved, but hardware complexity and cost increase
Solution Approach 1:
The patent merges ECC data transmission with application data transmission by storing both in the same DRAM page. The same I/O pins used for application data automatically transmit ECC data as well, eliminating the need for dedicated ECC I/O pins while maintaining error protection capability.
Solution Approach 2:
The patent makes existing I/O pins universally capable of transmitting both application data and ECC protection data. By organizing ECC data within the same page structure, the same physical pins serve dual functions, reducing hardware complexity while improving reliability.
Data Source
AI summary
One embodiment of the present invention sets forth a technique for protecting data with an error correction code (ECC). The data is accessed by a processing unit and stored in an external memory, such as dynamic random access memory (DRAM). Application data and related ECC data are advantageously stored in a common page within a common DRAM device. Application data and ECC data are transmitted between the processor and the external common DRAM device over a common set of input/output (I/O) pins. Eliminating I/O pins and DRAM devices conventionally associated with transmitting and storing ECC data advantageously reduces system complexity and cost.