DRAM ECC Memory Array Layout With Asymmetric Parity Access
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Solution Overview
Problem
The increasing shrinkage in fabrication design rules of dynamic random access memories (DRAMs) leads to rapid bit errors and decreased yield, compromising their reliability and performance.
Innovation Solution
A semiconductor memory device is designed with a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit, and a control logic circuit, where each bank array includes a normal cell region for data bits and a parity cell region for parity bits, allowing for asymmetric column access based on burst length multiples, enabling ECC encoding and decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fabrication design rules are shrunk to increase storage capacity, then memory density is improved, but bit error rate increases and yield decreases
Solution Approach 1:
The patent applies preliminary action by generating and storing parity bits before data is written to the memory cell array. The ECC engine performs encoding in advance, creating redundancy information that will be used later for error detection and correction during read operations. This proactive approach allows the system to combat bit errors that arise from fabrication shrinkage without requiring redesign of the memory cells themselves.
Solution Approach 2:
The patent changes the parameter of data organization by implementing asymmetric column access where data bits and parity bits are accessed with different burst lengths. Data bits use a first burst length while parity bits use a second burst length, allowing the system to optimize read operations for error correction efficiency. This parameter change enables more flexible and effective ECC operations.
2Productivity
If asymmetric column access is implemented for parity cell region, then ECC performance is improved, but access complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the column access operation into two distinct segments: one for data bits and one for parity bits. Each segment uses its own burst length parameter, allowing independent optimization. The I/O gating circuit separates the access paths, enabling the memory controller to manage data and parity bit transfers with different timing and burst parameters without interfering with each other.
Solution Approach 2:
The I/O gating circuit serves as an intermediary between the memory cell array and the ECC engine. It mediates the asymmetric column access by controlling the timing and burst length for data bit and parity bit transfers independently. This intermediary component simplifies the overall system architecture by centralizing the complexity of asymmetric access control in a dedicated circuit rather than distributing it throughout the memory controller.
Data Source
AI summary
A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes bank arrays, each of the bank arrays includes a first sub array and a second sub array, and each of the first sub array and the second sub array includes a normal cell region to store data bits and a parity cell region to store parity bits. The ECC engine generates the parity bits and corrects error bit. The I/O gating circuit is connected between the ECC engine and the memory cell array. The control logic circuit controls the I/O gating circuit to perform column access to the normal cell region according to a multiple of a burst length and to perform column access to the parity cell region according to a non-multiple of the burst length partially.