Partitioned DRAM Refresh Using Partial ECC for Fast Access
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Solution Overview
Problem
Dynamic random access memory (DRAM) devices consume significant power, especially during refresh operations, which limits battery life in portable electronic devices like cellular telephones, where frequent data access is required, making it impractical to use existing reduced power refresh modes that delay data access or minimize power savings.
Innovation Solution
Implementing an error checking and correcting semiconductor device that refreshes infrequently accessed data at a low rate using ECC techniques, while frequently accessed data is refreshed at a normal rate without ECC, allowing immediate access and reducing power consumption by partitioning the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If reduced power refresh mode is used to lower power consumption, then power savings are achieved, but data access is delayed
Solution Approach 1:
The memory array is divided into multiple banks, allowing selective refreshing of only those banks containing infrequently accessed data. Frequently accessed data in other banks can be accessed immediately without waiting for refresh operations, thus reducing the impact on data access time while still achieving power savings through selective low-rate refreshing of specific memory segments.
Solution Approach 2:
Different refresh rates are applied to different regions or banks of the memory array based on access patterns. Banks with infrequently accessed data are refreshed at a reduced rate to save power, while banks with frequently accessed data maintain normal refresh rates to ensure immediate availability, creating local quality differences in refresh behavior across the memory system.
2Use of energy by moving object
If refresh rate is reduced to save power, then power consumption decreases, but data retention reliability deteriorates
Solution Approach 1:
ECC (Error Correction Code) mechanisms are implemented to detect and correct data errors that may occur during low-rate refreshing. By preparing error correction capabilities in advance, the system can safely operate with reduced refresh rates for infrequently accessed data without compromising overall data retention reliability, as errors are corrected before they become critical failures.
Solution Approach 2:
Instead of applying reduced refresh rate uniformly to all memory, the system applies it partially only to banks containing infrequently accessed data. This partial application of low-rate refreshing combined with ECC protection allows power savings while maintaining reliability for the portion of data that requires it, and ensuring immediate availability for frequently accessed data that continues to be refreshed at normal rates.
Data Source
AI summary
A DRAM memory device includes several banks of memory cells each of which are divided into first and second sets of memory cells. The memory cells in the first set can be refreshed at a relatively slow rate to reduce the power consumed by the DRAM device. Error checking and correcting circuitry in the DRAM device corrects any data retention errors in the first set of memory cells caused by the relatively slow refresh rate. The memory cells in the second set are refreshed at a normal rate, which is fast enough that data retention errors do not occur. A mode register in the DRAM device may be programmed to select the size of the second set of memory cells.