DRAM Error Scrub Mode for On-Die ECC Transparency
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Solution Overview
Problem
In traditional memory subsystems, errors within DRAM devices can accumulate undetected due to on-die error checking and correction, as the host system lacks insight into error correction performed at the memory device level, leading to potential undetected error accumulation.
Innovation Solution
A memory device mode, referred to as error check and scrub (ECS) mode, is enabled to perform internal error checking and correction, count errors, and expose error information to the host system, allowing for transparency into error accumulation and improving system-level error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If on-die ECC logic is implemented to correct single bit failures, then error correction capability is improved, but error transparency to the host system deteriorates
Solution Approach 1:
An error information register is introduced as an intermediary component between the on-die ECC logic and the host system. This register stores error count information and makes it accessible to the host without interfering with the ECC correction process, thereby maintaining both error correction capability and error transparency.
Solution Approach 2:
The error monitoring function is segmented from the ECC correction function. The ECC logic continues to operate independently to correct errors, while a separate error information registration mechanism tracks and reports error counts to the host system, allowing both functions to coexist without compromising transparency.
2Productivity
If error checking and correction is performed internally at the memory device level, then error handling efficiency is improved, but system-level error visibility deteriorates
Solution Approach 1:
A feedback mechanism is established where the internal ECC logic provides error count information to an error information register, which in turn makes this information available to the host system. This allows the host to receive feedback about error conditions while the internal ECC processing continues efficiently.
Solution Approach 2:
The error information register serves as a mediator that bridges the internal ECC processing and the host system's error visibility requirements. It captures error information from the internal ECC logic and presents it to the host without disrupting the efficient internal error handling.
3Stability of the object's composition
If on-die ECC corrects errors automatically, then data integrity is improved, but error accumulation detection capability deteriorates
Solution Approach 1:
The error management functionality is segmented into two independent components: the ECC correction logic that maintains data integrity, and the error information register that detects and reports error accumulation. This segmentation allows both data integrity and error detection to function simultaneously without compromising either capability.
Solution Approach 2:
The error information register acts as an intermediary monitoring system that observes error events without interfering with the ECC correction process. It provides precise measurement of error accumulation while the ECC logic continues to maintain data integrity through automatic correction.
Data Source
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AI summary
An error check and scrub (ECS) mode enables a memory device to perform error checking and correction (ECC) and count errors. An associated memory controller triggers the ECS mode with a trigger sent to the memory device. The memory device includes multiple addressable memory locations, which can be organized in segments such as wordlines. The memory locations store data and have associated ECC information. In the ECS mode, the memory device reads one or more memory locations and performs ECC for the one or more memory locations based on the ECC information. The memory device counts error information including a segment count indicating a number of segments having at least a threshold number of errors, and a maximum count indicating a maximum number of errors in any segment.