DRAM ECC Interleaving Across Sub-Array Blocks for Bit Error Correction
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Solution Overview
Problem
The increasing bit errors and decreasing yield in DRAM devices due to reduced fabrication design rules pose challenges in semiconductor memory devices, particularly in volatile memory devices like DRAM, affecting their reliability and efficiency.
Innovation Solution
Implementing an error correction code (ECC) engine that generates parity data by interleaving sub data units across sub array blocks, enhancing error correction capabilities and maintaining reliability by correcting errors on a per-symbol basis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fabrication design rules are reduced to increase memory density, then storage capacity is improved, but bit error rate increases and yield decreases
Solution Approach 1:
The memory array is divided into multiple sub-array blocks, and data is segmented into sub-data units that are interleaved across these blocks. This segmentation allows error correction to be performed on a per-symbol basis rather than requiring correction of entire rows, thereby maintaining reliability while enabling higher density through reduced design rules.
Solution Approach 2:
An ECC engine is introduced as an intermediary component that performs error correction coding on data before it is stored in the memory array. The ECC engine generates parity data and interleaves sub-data units across multiple sub-array blocks, creating a protective layer that corrects bit errors without requiring larger design rules.
2Reliability
If traditional ECC encoding is used without interleaving, then error correction is provided, but complexity increases when multiple sub-array blocks are involved
Solution Approach 1:
The data is divided into sub-data units that are independently encoded and interleaved across sub-array blocks. This segmentation simplifies the ECC encoding process by allowing parallel processing of smaller data units rather than handling entire rows at once, reducing the complexity of the encoding operation while maintaining error correction capability.
Solution Approach 2:
The ECC engine performs preliminary interleaving of sub-data units across multiple sub-array blocks before the actual encoding and storage process. This preliminary organization of data simplifies subsequent encoding operations and facilitates more efficient error correction by pre-establishing the distributed structure needed for symbol-level correction.
3Ease of manufacture
If sub data units are stored in a single row without distribution, then storage simplicity is maintained, but error correction effectiveness decreases due to localized defects
Solution Approach 1:
Sub-data units are segmented and distributed across multiple sub-array blocks rather than being stored contiguously in a single row. This segmentation strategy maintains storage simplicity through regular addressing patterns while simultaneously improving error correction effectiveness by ensuring that localized defects in one sub-array block do not corrupt entire data units.
Solution Approach 2:
The storage structure transitions from a single-dimensional row-based organization to a multi-dimensional distributed structure across multiple sub-array blocks. This dimensional change allows data to be spread across different physical locations in the memory array, enabling more effective error correction while maintaining manageable storage complexity through systematic addressing.
Data Source
AI summary
A memory system includes a semiconductor memory device and a memory controller to control the semiconductor memory device. The semiconductor memory device includes a memory cell array that is divided into a plurality of sub array blocks arranged in a first direction and a second direction. The memory controller includes an error correction code (ECC) engine. The ECC engine, in a write operation, generates a parity data by performing an ECC encoding on a user data including a plurality of sub data units, generates a main data by interleaving the sub data units based on mapping information such that two sub data units to be stored in one row of a target sub array block are included in one symbol. The mapping information indicates a mapping relationship between the plurality of sub data units and rows of the target sub array block storing the plurality of sub data units.