DRAM ECC Syndrome Recovery for Sequential Bit Error Correction
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Solution Overview
Problem
The increasing bit errors in dynamic random-access memories (DRAMs) due to reduced fabrication design rules have led to decreased yield and a need for enhanced credibility in semiconductor memory devices.
Innovation Solution
A semiconductor memory device incorporating a memory cell array, an error correction code engine (ECC engine), an input/output gating circuit, an error information register, and a control logic circuit that stores error addresses and syndromes associated with error bits, allowing for the recovery and correction of error bits through ECC decoding and syndrome association.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fabrication design rules are reduced to increase memory density, then memory capacity is improved, but bit error rate increases
Solution Approach 1:
The patent performs preliminary error detection and correction by storing syndrome information in an error information register during initial read operations. When subsequent reads detect errors, the stored syndrome is retrieved and used to correct the errors, preventing error propagation and maintaining data integrity despite increased bit error rates from scaled fabrication
Solution Approach 2:
The system implements feedback by continuously monitoring read operations, storing error patterns in the error information register, and using this feedback information to correct future errors. The control logic circuit creates a closed-loop system where error information from previous operations informs correction actions in subsequent operations, effectively combating the increased error rates from reduced fabrication rules
2Reliability
If ECC decoding is performed on every read operation to correct errors, then reliability is improved, but operation speed decreases
Solution Approach 1:
Instead of performing full ECC decoding on every read operation, the patent applies partial correction by first checking for errors and only performing correction when errors are detected. The system performs minimal verification on normal reads and applies comprehensive ECC decoding only when necessary, reducing the average time penalty while maintaining high reliability
Solution Approach 2:
The system performs preliminary error detection and stores syndrome information in advance in the error information register. When errors are detected in subsequent reads, the pre-stored syndrome information is immediately retrieved and used for correction, eliminating the need to recalculate syndromes and significantly accelerating the error correction process
3Productivity
If error information register is used to store syndrome information, then error correction efficiency is improved, but device complexity increases
Solution Approach 1:
The patent creates a simplified copy of the syndrome information in the error information register, which is a compact storage structure that mirrors only the essential error detection data. This copy allows rapid retrieval and processing without requiring the full complexity of the original ECC decoding circuitry, maintaining high correction efficiency while minimizing added complexity
Solution Approach 2:
The error information register serves multiple functions: it stores syndrome information for error correction, tracks error patterns for reliability monitoring, and provides input for control logic decisions. This multi-functionality consolidates what could be separate complex circuits into a single versatile component, improving efficiency without proportionally increasing overall device complexity
Data Source
AI summary
A semiconductor memory device is provided. The device includes a memory cell array including a plurality of dynamic memory cells; an error correction code (ECC) engine; an input/output (I/O) gating circuit connected between the ECC engine and the memory cell array; an error information register configured to store an error address and a first syndrome, the error address and the first syndrome being associated with a first error bit in a first codeword stored in a first page of the memory cell array; and a control logic configured to, based on the first codeword being read again and including a second error bit which is different from the first error bit, recover a second syndrome associated with the second error bit by using the first syndrome stored in the error information register and sequentially correct the first error bit and the second error bit.