DRAM ECC Syndrome Reuse for Sequential Bit Error Correction
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Solution Overview
Problem
The increasing bit errors in dynamic random-access memories (DRAMs) due to reduced fabrication design rules have led to decreased yield and a need for enhanced credibility in semiconductor memory devices.
Innovation Solution
A semiconductor memory device incorporating a memory cell array, an error correction code engine (ECC engine), an input/output gating circuit, an error information register, and a control logic circuit that stores error addresses and syndromes associated with error bits, allowing for the recovery and correction of error bits through ECC decoding and syndrome association.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fabrication design rules are reduced to increase memory density, then memory capacity is improved, but bit error rate increases and yield decreases
Solution Approach 1:
The patent performs preliminary error detection and correction by storing syndrome information in error information registers during initial read operations. When subsequent errors occur in the same codeword, the stored syndrome is reused to accelerate correction, preventing error propagation and maintaining data integrity despite increased bit error rates from scaled fabrication
Solution Approach 2:
The system implements feedback by monitoring error patterns through syndrome calculation and storing them in error information registers. This feedback mechanism allows the ECC engine to learn from previous errors and apply targeted corrections to subsequent errors in the same codeword, effectively managing the increased bit error rate resulting from reduced fabrication design rules
2Reliability
If ECC decoding is performed on every read operation to correct errors, then data reliability is improved, but operation time increases
Solution Approach 1:
The patent performs preliminary syndrome calculation and error detection during the initial read operation, storing the syndrome information in error information registers. This preliminary action enables subsequent reads of the same codeword to reuse the stored syndrome, avoiding redundant full ECC decoding operations and reducing operation time while maintaining data correctness
Solution Approach 2:
Instead of performing complete ECC decoding on every read operation, the system applies partial action by reusing previously calculated syndromes for subsequent errors in the same codeword. This selective approach corrects errors efficiently without repeating unnecessary decoding steps, reducing operation time while ensuring data correctness through targeted error correction
Data Source
AI summary
A semiconductor memory device is provided. The device includes a memory cell array including a plurality of dynamic memory cells; an error correction code (ECC) engine; an input/output (I/O) gating circuit connected between the ECC engine and the memory cell array; an error information register configured to store an error address and a first syndrome, the error address and the first syndrome being associated with a first error bit in a first codeword stored in a first page of the memory cell array; and a control logic configured to, based on the first codeword being read again and including a second error bit which is different from the first error bit, recover a second syndrome associated with the second error bit by using the first syndrome stored in the error information register and sequentially correct the first error bit and the second error bit.