DRAM ECC Integrity Checking Through Parity-Mismatch Test Writes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing DRAM ECC circuits are not thoroughly tested, leading to incomplete error coverage and potential integrity issues, as current testing methods fail to evaluate all ECC paths and do not utilize data patterns to generate parity check bits.
Innovation Solution
A new testing method is introduced that includes a special write protocol where data is written to DRAM without calculating parity bits, allowing for the generation of error patterns to test the entire ECC circuit path, including the DRAM and SoC, by comparing parity bits and calculating syndromes to detect and correct errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC testing methods are used, then testing process is simple, but error coverage is incomplete and certain ECC paths are not tested
Solution Approach 1:
The testing process is divided into multiple phases: initial ECC testing, special write operations to create error patterns, and verification operations. This segmentation allows comprehensive testing of all ECC paths by breaking down the complex testing into manageable steps that systematically cover different error scenarios.
Solution Approach 2:
The patent applies preliminary action by first writing correct data to DRAM and calculating proper parity bits before introducing errors. The special write operation pre-establishes error patterns by writing data without calculating parity bits, creating known error conditions that can be detected and verified in subsequent operations.
2Reliability
If all ECC paths are tested thoroughly, then error detection capability is improved, but testing time and operations increase
Solution Approach 1:
The ECC circuit performs self-testing by using its own parity calculation capability to verify error detection. The system writes data, calculates parity bits, intentionally introduces errors through special write operations, then uses the same parity calculation mechanism to detect and verify the errors, making the ECC circuit self-verify without external testing equipment.
Solution Approach 2:
The patent changes the parameter of parity bit calculation by enabling and disabling it during different operations. During normal operations, parity bits are calculated; during special write operations for testing, parity bit calculation is disabled to create error patterns. This parameter change allows the same hardware to serve both normal data storage and comprehensive error detection testing.
Data Source
AI summary
Implementations herein describe a system including a system-on-chip including at least a host and a dynamic random-access memory (DRAM) in communication with the SoC, the DRAM including at least an error correction code engine, the system configured to allow the host to write first data to the DRAM, calculate parity bits for the first write data, store the first write data and the parity bits in a DRAM core of the DRAM, allow the host to write second data to the DRAM, store the second write data in the DRAM core without calculating parity bits for the second write data, enable the DRAM to calculate parity bits of the second write data and compare the parity bits of the second write data to the parity bits of the first write data, and calculate a syndrome based on a comparison to correct errors detected in the DRAM core.