DRAM Erasure Error Correction for Low-Power Refresh Retention
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Solution Overview
Problem
Current DRAM devices face high power consumption during refresh operations, which affects battery life in portable electronic devices, and existing error correction methods are complex and not suitable for implementation in these devices.
Innovation Solution
Implementing an erasure error correction method that uses a simplified algorithm to correct errors in DRAM devices, allowing for reduced power consumption by prolonging the power-off period during refresh operations and using error correcting circuitry to detect and correct errors in a low-power data retention mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the refresh rate of DRAM memory cells is lowered to reduce power consumption, then power consumption during refresh is reduced, but the risk of data loss increases due to charge leakage
Solution Approach 1:
The patent applies preliminary action by performing error correction decoding before the refresh operation is completed. The ECC decoder detects and corrects errors in data bits during the refresh cycle, specifically targeting double-bit errors that may occur due to extended retention periods. This preliminary error correction ensures data integrity even when refresh rates are reduced, allowing the system to lower refresh frequency without sacrificing reliability.
2Reliability
If complex error correction circuitry is implemented to correct errors at lower refresh rates, then data retention reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the error correction process into distinct stages: first performing single-bit error correction, then identifying and correcting double-bit errors in specific locations. The ECC decoder is segmented to handle different error types separately, with specific logic for detecting and correcting double-bit errors in data bits versus syndrome bits. This segmented approach reduces overall circuit complexity compared to implementing a single comprehensive error correction mechanism.
Solution Approach 2:
The patent applies partial action by implementing error correction only for specific error conditions rather than all possible errors. The system focuses on correcting single-bit errors and double-bit errors in data bits, while using different strategies for syndrome bit errors. The refresh operation is partially performed with extended intervals for certain memory cells that have been identified as having errors, rather than uniformly refreshing all cells at high frequency.
3Reliability
If conventional redundancy circuitry is used to repair defective memory cells, then manufacturing yield is improved, but device complexity and area increase
Solution Approach 1:
The patent applies copying by using syndrome bits as copies of error information to identify and correct data bit errors. The ECC decoder generates syndrome bits that are copies of the error patterns present in the data, allowing the system to detect and correct errors without physically replacing defective memory cells. This virtual copying approach through syndrome calculation avoids the need for complex physical redundancy circuitry and cell replacement mechanisms.
Data Source
AI summary
Data bits stored in memory cells are recognized by an ECC generator as data bit strings in a first direction and data bit strings in a second direction such that each data bit string in the first direction and each data bit string in the second direction share one data bit in common. The ECC controller identifies a data bit string in the first direction having more than one data bit in error based on a respective correction code in the first direction and identifies a data bit string in the second direction having more than one data bit in error based on a respective correction code in the second direction, and causes the data bit shared by the identified data bit string in the first direction and the identified data bit string in the second direction to be changed.