DRAM Error Injection System for ECC Validation
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Solution Overview
Problem
As memory systems become smaller and more dense, the likelihood of cell-level errors due to leakage increases, necessitating effective error correction mechanisms during manufacturing and design.
Innovation Solution
An error injection system is implemented within the dual-inline memory storage module (DIMM) system to inject controlled errors into DRAMs, utilizing a programmable error control table to test the error correction capabilities of the ECC memory, ensuring reliable operation by validating error correction at a finer level than the entire memory system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory structures are made smaller and more dense to increase storage capacity, then memory storage capacity increases, but the probability of cell level error due to leakage increases
Solution Approach 1:
The patent implements preliminary error detection and correction by incorporating ECC (Error Correcting Code) mechanisms during the manufacturing and design testing phases. Error detection circuits are built into the memory structure to proactively identify and correct cell-level errors before they affect system operation, addressing the reliability issue that arises from increased density.
2Reliability
If ECC memory is implemented to correct errors, then error correction capability is improved, but the complexity of the memory system increases
Solution Approach 1:
The patent merges the error correction functionality directly into the memory controller and memory array structure. The ECC logic is integrated with the existing memory interface and control circuits, allowing error correction to be performed as part of the normal memory read/write operations without requiring separate dedicated correction circuits, thus reducing overall system complexity.
3Reliability
If memory systems are tested during manufacture to ensure reliable operation, then reliability is improved, but the testing time and complexity increase
Solution Approach 1:
The patent implements self-testing capabilities within the memory system where the memory controller automatically performs error detection and correction operations during normal operation and manufacturing tests. The built-in ECC circuits autonomously identify and correct errors without requiring external test equipment or manual intervention, reducing testing time and complexity while ensuring reliable operation.
Data Source
AI summary
One example includes a system. The system includes an error injection system. The error injection system includes an error injector to store a programmable control structure to define a memory error. The error injector being further used to inject the memory error into a respective one of a plurality of memory storage elements associated with a memory system at a predetermined address via an address controller and to determine if the memory error at the predetermined address associated with the respective one of the plurality of memory storage elements is corrected via error-correcting code (ECC) memory associated with the memory system.