DRAM Error Scrub Mode for On-Die ECC Transparency
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Solution Overview
Problem
Traditional memory subsystems fail to detect and correct errors accumulated within DRAM devices due to on-die ECC, leading to undetected errors that can impact system reliability and data integrity.
Innovation Solution
Implementing an Error Check and Scrub (ECS) mode in memory devices that allows for internal error monitoring and correction, enabling the counting of error segments and tracking of the segment with the highest error count, and exposing this information to the host system for improved system-level error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If on-die ECC logic is implemented in DRAM devices, then single bit failures can be corrected, but errors accumulate undetected by the host system
Solution Approach 1:
The patent implements a feedback mechanism where the memory device sends error status information back to the host system. The host receives notifications about error conditions through status registers and interrupt signals, creating a closed-loop system that maintains error transparency while preserving the benefits of on-die ECC correction
Solution Approach 2:
The patent introduces an intermediary error status register and control logic that bridges the memory device and host system. This intermediary structure captures error information from the on-die ECC logic and makes it visible to the host, allowing the system to monitor error accumulation without interfering with the correction process
2Measurement precision
If error checking and monitoring are performed continuously, then error detection capability is improved, but power consumption and system complexity increase
Solution Approach 1:
The patent implements periodic error checking through self-refresh cycles rather than continuous monitoring. During self-refresh, the memory device periodically reads and validates stored data, detecting errors without requiring continuous host intervention or additional complex monitoring circuitry
Solution Approach 2:
The memory device performs self-diagnosis and error detection during its own operational cycles, particularly during self-refresh modes. This self-service approach allows the memory to monitor its own health status without adding external complexity or consuming additional system resources
Data Source
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AI summary
An error check and scrub (ECS) mode enables a memory device to perform error checking and correction (ECC) and count errors. An associated memory controller triggers the ECS mode with a trigger sent to the memory device. The memory device includes multiple addressable memory locations, which can be organized in segments such as wordlines. The memory locations store data and have associated ECC information. In the ECS mode, the memory device reads one or more memory locations and performs ECC for the one or more memory locations based on the ECC information. The memory device counts error information including a segment count indicating a number of segments having at least a threshold number of errors, and a maximum count indicating a maximum number of errors in any segment.