DRAM Fast Exit from Self-Refresh Mode
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Solution Overview
Problem
Current DRAM devices require a significant wait period (tXS) before issuing commands due to the internal self-refresh mode, which increases with device density, leading to inefficiencies in memory access.
Innovation Solution
Enabling the DRAM device to abort the self-refresh mode allows for a faster exit, reducing the wait period by using a 'fast exit' mode initiated by the memory controller, enabling a clock signal to abort the self-refresh mode and maintaining the option for a full self-refresh cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the DRAM device operates in self-refresh mode to maintain data validity, then data retention is improved, but the exit time (tXS) increases significantly
Solution Approach 1:
The patent applies preliminary action by initiating the exit from self-refresh mode before the actual data access is needed. The memory controller sends an early exit command that starts the refresh process in advance, allowing the system to prepare for data access without waiting for the full tRFC period to elapse naturally. This reduces the effective wait time while ensuring data validity is maintained.
Solution Approach 2:
The patent implements dynamics by making the self-refresh exit time variable rather than fixed. The system can dynamically adjust the exit timing based on whether a fast exit is requested, allowing the DRAM to transition between different exit modes (normal vs. fast) depending on system needs. This dynamic approach allows optimization between data retention and access speed.
2Quantity of substance
If DRAM devices increase in density to improve storage capacity, then storage capacity is improved, but the tRFC and tXS values increase
Solution Approach 1:
The patent applies preliminary action by initiating the exit from self-refresh mode before the actual data access is needed. The memory controller sends an early exit command that starts the refresh process in advance, allowing the system to prepare for data access without waiting for the full tRFC period to elapse naturally. This reduces the effective wait time while ensuring data validity is maintained.
Solution Approach 2:
The patent implements parameter changes by modifying the operational parameters of the DRAM device during self-refresh mode. Specifically, it changes the refresh timing parameters by allowing an early exit from self-refresh before the standard tRFC period completes. This parameter adjustment enables faster response times while adapting to high-density device characteristics.
3Reliability
If the memory controller waits for the complete refresh cycle before issuing commands, then data validity is ensured, but the memory access efficiency decreases
Solution Approach 1:
The patent applies preliminary action by initiating the exit from self-refresh mode before the actual data access is needed. The memory controller sends an early exit command that starts the refresh process in advance, allowing the system to prepare for data access without waiting for the full tRFC period to elapse naturally. This reduces the effective wait time while ensuring data validity is maintained.
Solution Approach 2:
The patent implements feedback by establishing a communication mechanism between the memory controller and the DRAM device. The controller can send early exit commands based on system state feedback, and the DRAM device provides feedback about its refresh status. This feedback loop enables the controller to make informed decisions about when to issue commands, optimizing both data validity and access efficiency.
Data Source
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AI summary
Embodiments of the invention describe a dynamic random access memory (DRAM) device that may abort a self-refresh mode to improve the exit time from a DRAM low power state of self-refresh. During execution of a self-refresh mode, the DRAM device may receive a signal (e.g., a device enable signal) from a memory controller operatively coupled to the DRAM device. The DRAM device may abort the self-refresh mode in response to receiving the signal from the memory controller.