DRAM ECC Flag Bit Tracking for Reduced-Power Refresh
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Solution Overview
Problem
Existing memory devices, such as DRAM, consume significant power during refresh operations, which limits battery life in portable electronic devices, and current error correction techniques increase latency and power consumption by requiring frequent syndrome generation and storage, even when data has not changed.
Innovation Solution
An ECC method and system that uses a flag bit to determine if data has been modified since the last refresh, allowing for reduced power refresh modes and efficient error checking and correction by generating and storing syndromes only when necessary, thereby reducing unnecessary power consumption and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DRAM memory cells are refreshed at a high rate to prevent data loss, then data reliability is improved, but power consumption increases
Solution Approach 1:
The patent applies partial action by refreshing only the subset of memory cells that actually need refreshing, rather than refreshing all memory cells at the traditional high rate. The refresh rate is dynamically adjusted for each memory cell based on its individual charge leakage characteristics, allowing some cells to be refreshed more frequently while others less frequently, thereby reducing overall power consumption while maintaining data reliability.
2Reliability
If ECC syndrome generation and storage is performed for all data groups during refresh, then data error correction capability is improved, but power consumption and latency increase
Solution Approach 1:
The patent applies partial action by generating and storing ECC syndromes only for data groups that have been modified since the last refresh operation, rather than performing ECC operations on all data groups. This selective approach significantly reduces the power consumption and latency associated with ECC operations while maintaining the ability to correct errors in modified data.
Solution Approach 2:
The patent implements a self-service mechanism where the system automatically tracks which data groups have been modified using a modification status bit, and autonomously determines which ECC syndrome generation operations are necessary. This eliminates the need for comprehensive ECC operations on all data, allowing the system to service only the specific data groups that require error correction.
3Reliability
If comprehensive ECC syndrome generation is performed for all data, then data integrity is improved, but processing time and latency increase
Solution Approach 1:
The patent applies partial action by performing ECC syndrome generation only for modified data groups rather than all data groups. The modification status bit tracks which data has changed, allowing the system to skip ECC operations on unchanged data and focus only on data that requires integrity verification, thereby reducing processing time and latency.
Data Source
AI summary
A DRAM device includes an ECC generator/checker that generates ECC syndromes corresponding to items of data stored in the DRAM device. The DRAM device also includes an ECC controller that causes the ECC syndromes to be stored in the DRAM device. The ECC controller also causes a flag bit having a first value to be stored in the DRAM device when a corresponding ECC syndrome is stored. The ECC controller changes the flag bit to a second value whenever the corresponding data bits are modified, this indicating that the stored syndrome no longer corresponds to the stored data. In such case, the ECC controller causes a new ECC syndrome to be generated and stored, and the corresponding flag bit is reset to the first value. The flag bits may be checked in this manner during a reduced power refresh to ensure that the stored syndromes correspond to the stored data.