DRAM ECC Flag Bits for Selective Syndrome Refresh
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Solution Overview
Problem
Existing memory systems face challenges in reducing power consumption during refresh operations in DRAM devices, as current error correction techniques require significant time and power to generate and store syndromes, leading to increased latency and power usage, especially when entering or exiting reduced power refresh modes.
Innovation Solution
The implementation of an ECC method and system that uses a flag bit to determine if data has been modified since the last refresh, allowing for the generation and storage of new syndromes only when necessary, thereby reducing the need for frequent syndrome generation and storage, and enabling efficient data integrity checking and correction during both reduced power refresh and normal operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ECC syndrome generation and storage is performed for every refresh operation, then data integrity is maintained, but power consumption increases significantly
Solution Approach 1:
Instead of performing full ECC syndrome generation and storage for every refresh operation, the patent applies partial action by only generating and storing syndromes when data is actually modified. The system selectively performs ECC operations based on whether write operations have occurred since the last refresh, thereby reducing unnecessary syndrome generation and storage while still maintaining data integrity for modified data.
2Use of energy by moving object
If refresh rate is reduced to lower power consumption, then power usage decreases, but data loss risk increases
Solution Approach 1:
The patent applies preliminary action by generating and storing ECC syndromes in advance when data is written or modified, before the actual refresh operation occurs. This allows the system to use these pre-generated syndromes during reduced-power refresh operations to detect and correct errors, thereby maintaining data retention reliability even when refresh rates are reduced to lower power consumption.
3Reliability
If syndrome generation is performed frequently to ensure data correctness, then data integrity is improved, but latency increases
Solution Approach 1:
The patent reduces latency by applying partial action - only performing syndrome generation and storage when data modifications are detected via the dirty bit mechanism. This selective approach avoids the time-consuming full syndrome generation for every refresh operation, thereby reducing latency while still ensuring data correctness for modified data through targeted ECC operations.
Data Source
AI summary
A DRAM device includes an ECC generator/checker that generates ECC syndromes corresponding to items of data stored in the DRAM device. The DRAM device also includes an ECC controller that causes the ECC syndromes to be stored in the DRAM device. The ECC controller also causes a flag bit having a first value to be stored in the DRAM device when a corresponding ECC syndrome is stored. The ECC controller changes the flag bit to a second value whenever the corresponding data bits are modified, this indicating that the stored syndrome no longer corresponds to the stored data. In such case, the ECC controller causes a new ECC syndrome to be generated and stored, and the corresponding flag bit is reset to the first value. The flag bits may be checked in this manner during a reduced power refresh to ensure that the stored syndromes correspond to the stored data.