DRAM Capacitor Electrode Structure With Flared Contact Openings
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Solution Overview
Problem
In dynamic random access memory (DRAM) devices, establishing effective electrical connections between memory cells becomes increasingly difficult as device density increases, leading to potential short circuits and poor connections due to varying structural designs and capacitor structures.
Innovation Solution
The semiconductor memory device omits the storage node pad between the capacitor structure and the storage node contact, using a sacrificial layer to form expanding portions at the electrode layer, enhancing connection and capacitance while simplifying the manufacturing process by avoiding over-etching issues and omitting conductive pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the storage node pad is disposed between the capacitor structure and the storage node contact, then the connection is established, but the device complexity and manufacturing process complexity increase
Solution Approach 1:
The patent removes the storage node pad from the device structure, extracting this intermediate component that previously connected the capacitor structure to the storage node contact. This simplification is achieved by directly connecting the capacitor structure to the storage node contact through an opening, eliminating the need for the separate pad structure and reducing overall device complexity while maintaining electrical connection functionality
Solution Approach 2:
The patent merges the functions of the storage node pad and the storage node contact into a single integrated structure. The storage node contact is designed to directly receive and establish electrical connection with the capacitor structure, combining what were previously separate functional elements (pad for connection + contact for electrical pathway) into one unified component, thereby reducing device complexity
2Reliability
If the storage node pad is disposed between the capacitor structure and the storage node contact, then the connection is established, but the manufacturing process becomes more complex with additional steps
Solution Approach 1:
The manufacturing process is simplified by extracting and removing the formation steps for the storage node pad. The patent eliminates the need to deposit, pattern, and etch separate pad structures, instead focusing on forming a single opening that directly exposes the storage node contact to the capacitor structure, thereby reducing the number of manufacturing steps and improving ease of manufacture
Solution Approach 2:
The patent applies preliminary action by pre-forming the storage node contact structure and the opening in such a way that the capacitor structure can be directly connected without requiring subsequent pad formation steps. The opening is configured in advance to expose the storage node contact, eliminating the need for additional manufacturing steps that would otherwise be required to create the intermediate pad connection
3Ease of manufacture
If the opening of the capacitor structure is formed without a stop layer, then the process is simplified, but over-etching issues occur
Solution Approach 1:
The patent introduces a sacrificial layer as an intermediary element during the opening formation process. This sacrificial layer serves as a temporary stop layer that prevents over-etching of the storage node contact, and is subsequently removed after serving its protective function. The intermediary sacrificial layer enables precise etching control without requiring permanent structural modifications, thus maintaining manufacturing precision while preserving process simplicity
4Productivity
If the capacitor structure has insufficient bottom area, then the device density is high, but the connection reliability and capacitance are poor
Solution Approach 1:
The patent extends the storage node contact structure vertically in the third dimension to increase its bottom area for better connection with the capacitor structure. Instead of expanding the contact area in the planar (2D) direction which would reduce device density, the contact is extended downward into the vertical dimension, providing increased surface area for reliable electrical connection while maintaining high device density in the lateral direction
Data Source
AI summary
A semiconductor memory device and a method of forming the same are provided, with the semiconductor memory device including a substrate, a stacked structure, plural openings, plural flared portions and an electrode layer. The stacked structure is disposed on the substrate and includes alternately stacked oxide material layers and stacked nitride material layers. Each of the openings is disposed in the stacked structure, and each of the flared portions is disposed under each of the openings, in connection with each opening. The electrode layer is disposed on surfaces of each opening and each flared portion.