DRAM FPGA Module with Dynamic Reconfigurable Logic
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Solution Overview
Problem
Conventional memory hierarchies in data-center and mobile-device applications are inefficient due to high costs and sub-optimal performance when implementing accelerator logic close to memory, as they degrade the maximum efficiency of processing accelerators and forfeit DRAM capacity.
Innovation Solution
A system architecture utilizing dynamic random access memory field programmable gate arrays (DRAM-FPGAs) that selectively reconfigure DRAM arrays to behave like look-up tables or traditional DRAM, allowing for reconfigurable logic close to memory, reducing power requirements and increasing density and flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If accelerator logic is implemented close to memory (DRAM), then performance and energy efficiency are improved, but DRAM capacity is forfeited and manufacturing cost increases
Solution Approach 1:
The patent implements dynamically reconfigurable logic within DRAM arrays, allowing memory cells to switch between storage and logic operations at runtime. This dynamic transformation enables the same physical resources to serve multiple functions, improving performance without permanently sacrificing DRAM capacity.
Solution Approach 2:
The patent creates multi-functional DRAM cells that can operate as either memory storage or logic processing elements depending on configuration. This universality allows a single DRAM array to provide both high-speed storage and accelerated computing functions, resolving the trade-off between capacity and performance.
2Use of energy by moving object
If accelerator logic is implemented close to memory (DRAM), then energy efficiency is improved, but manufacturing cost increases
Solution Approach 1:
The patent merges memory and logic functions into a single integrated structure using standard DRAM fabrication processes. By combining these functions at the architectural level rather than requiring separate manufacturing processes, the design achieves energy efficiency of near-memory computing without significantly increasing manufacturing complexity or cost.
3Quantity of substance
If conventional memory hierarchy is used, then DRAM capacity is maintained, but performance and energy efficiency are degraded
Solution Approach 1:
The patent introduces dynamic reconfiguration capability that allows DRAM arrays to switch between traditional memory mode and logic processing mode. This maintains full DRAM capacity when needed while enabling accelerated computing performance when computational tasks are detected, eliminating the need to choose between capacity and performance.
4Productivity
If reconfigurable logic is integrated onto DRAM die, then performance is improved, but DRAM capacity is reduced
Solution Approach 1:
The patent changes the operational parameters of DRAM cells to enable logic operations. By modifying how DRAM cells are configured and accessed rather than adding separate logic components, the system achieves reconfigurable logic functionality while maintaining the same physical DRAM capacity, as the same cells serve different functions at different times.
Data Source
AI summary
An accelerator controller comprises a detector and a loader. The detector detects runtime features of an application or a virtual machine and identifies an accelerator logic associated with the application or the virtual machine corresponding to the detected runtime features. The loader loads the identified accelerator logic into at least one dynamic random access memory (DRAM). The at least one DRAM array is selectively reconfigurable to behave like a look-up table (LUT) or to behave like a DRAM memory array based on the identified accelerator logic, and the at least one DRAM array is in a cache-coherent address space of the operating system environment. The accelerator logic may comprise a look-up table (LUT).