DRAM FSP Temperature Control for Stable High-Frequency Operation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing semiconductor memory devices, particularly DRAMs used in automotive environments, face challenges in maintaining optimal operation across a wide range of temperatures and frequencies, leading to performance issues and reliability concerns.

Innovation Solution

A memory device and system-on-chip configuration that includes a temperature monitoring circuit and FSP operation modes, allowing the SoC to control the memory device based on current frequency and temperature ranges, with trained FSP data sets optimizing operating parameters for various environments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a DRAM is designed to operate in automotive environments with wide temperature ranges, then the operating temperature range is improved, but performance stability and reliability deteriorate due to extreme temperature variations affecting memory cell operation

Engineering Contradiction:
Improveoperating temperature rangeVSAvoidperformance stability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent implements dynamic adjustment of memory device operating parameters based on real-time temperature monitoring. The system transitions from static fixed parameters to dynamic adaptive parameters that change with temperature conditions, allowing the memory device to maintain optimal performance across wide temperature ranges by adjusting parameters such as refresh rates, write levels, and read thresholds according to current temperature conditions

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes physical operating parameters of the memory device in response to temperature variations. Multiple frequency set point (FSP) data sets are stored, each optimized for specific temperature ranges and operation frequencies. The system selects and applies the appropriate FSP data set based on current temperature and frequency conditions, thereby maintaining reliability while adapting to extreme environmental conditions

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the memory device operates at high frequencies, then productivity is improved, but reliability deteriorates due to increased sensitivity to temperature variations and signal integrity issues

Engineering Contradiction:
Improveoperation frequencyVSAvoidoperation stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements dynamic adjustment of memory device operating parameters based on real-time temperature monitoring. The system transitions from static fixed parameters to dynamic adaptive parameters that change with temperature conditions, allowing the memory device to maintain optimal performance across wide temperature ranges by adjusting parameters such as refresh rates, write levels, and read thresholds according to current temperature conditions

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes physical operating parameters of the memory device in response to temperature variations. Multiple frequency set point (FSP) data sets are stored, each optimized for specific temperature ranges and operation frequencies. The system selects and applies the appropriate FSP data set based on current temperature and frequency conditions, thereby maintaining reliability while adapting to extreme environmental conditions

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250370628A1Memory device, system-on-chip configured to control memory device, and electronic device including the same
Publication Date: 2025.12.04 SAMSUNG ELECTRONICS CO LTD
  • US20250370628A1 patent drawing
  • US20250370628A1 patent drawing
  • US20250370628A1 patent drawing

AI summary

Disclosed is an electronic device that includes a memory device operating in a current frequency set point (FSP) operation mode among FSP operation modes and a system-on-chip (SoC) controlling the memory device. The memory device includes FSP mode register sets storing FSP data sets respectively corresponding to the FSP operation modes, and a temperature monitoring circuit monitoring a temperature range of the memory device. The SoC controls the current FSP operation mode based on a current operation frequency of the memory device and a current temperature range of the memory device. The FSP operation modes include a first FSP operation mode for an operation of the memory device at a first operation frequency and a first temperature range, and a second FSP operation mode for an operation of the memory device at the first operation frequency and a second temperature range higher than the first temperature range.