DRAM Gate Oxide Layout for GIDL Leakage Reduction
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Solution Overview
Problem
As DRAM devices shrink, cell capacitance decreases, leading to increased cell leakage due to access device gate-induced drain leakage (GIDL), which affects the reliability of dynamic random-access memory (DRAM) devices.
Innovation Solution
The integration of directional deposition and etch technologies is used to locally replace the original gate oxide in the poly-silicon gate region with a CVD oxide of lower dielectric constant (low-k) without impacting the wordline metal region, reducing the electric field and suppressing GIDL leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM size is reduced to increase cell capacitance, then storage capacity is improved, but GIDL leakage increases
Solution Approach 1:
The patent applies different dielectric constant values to different spatial regions of the gate oxide. Specifically, the gate oxide has a first dielectric constant in the wordline region and a second dielectric constant in the bitline region, with the second being lower than the first. This local differentiation allows the bitline region to suppress GIDL leakage while the wordline region maintains its electrical characteristics.
Solution Approach 2:
The patent changes the dielectric constant parameter of the gate oxide material to control GIDL leakage. By selecting materials with appropriate dielectric constants for different regions (higher in wordline, lower in bitline), the patent optimizes both storage capacity and leakage suppression without changing the overall device structure.
2Object-generated harmful factors
If gate oxide is replaced with low-k material to suppress GIDL, then leakage is reduced, but wordline gate oxide may be impacted
Solution Approach 1:
The patent implements spatially differentiated gate oxide properties where the wordline region maintains its original gate oxide with higher dielectric constant for reliable gate control, while the bitline region uses low-k material with lower dielectric constant to suppress GIDL. This local quality differentiation resolves the contradiction by applying material optimization only where needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces GIDL leakage by lowering the electric field in the poly-silicon gate region, enhancing the reliability of DRAM devices without introducing additional processing steps that could increase interface defects.
Implementation Method 1
replace the original gate oxide in the poly-silicon gate region with a lower dielectric constant (low-k) CVD oxide, reducing the electric field and suppressing GIDL leakage
Data Source
AI summary
Approaches for reducing GIDL are disclosed. In one example, a method of forming a DRAM device may include forming a trench in a substrate layer, providing a first gate oxide layer along a sidewall and a bottom surface of the trench, and forming a first gate material within the trench. The method may further include removing the first gate oxide layer along an upper portion of the sidewall of the trench by delivering ions into the upper portion of the trench at a non-zero angle relative to a perpendicular extending from an upper surface of the substrate layer, and forming a second gate oxide layer along the upper portion of the sidewall of the trench, wherein a first dielectric constant of the first gate oxide layer is greater than a second dielectric constant of the second gate oxide layer.