DRAM GIO Line Segmentation With Repeaters for Faster Bank Access
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Solution Overview
Problem
High-density DRAMs with multiple banks face increased chip size and deteriorated address access time due to extended global input/output (GIO) lines, leading to longer data loading times and higher current consumption.
Innovation Solution
The implementation of a high-density semiconductor device with a repeater system that separates the global input/output line into core and Peri-area segments, using repeaters to exchange data between these segments in response to read or write commands, reducing the total length of the GIO line and eliminating the need for multiple GIO lines per operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the DRAM has at least 8 banks, then the chip density is improved, but the GIO line length is greatly extended, resulting in deteriorated address access time characteristics
Solution Approach 1:
The patent divides the single long GIO line into multiple segment GIO lines (first GIO line and second GIO line), each serving specific banks. This segmentation reduces the length of each individual GIO line segment while maintaining connectivity to all 8 banks, thereby resolving the contradiction between high chip density and excessive GIO line length.
2Adaptability or versatility
If the GIO line length is extended, then more banks can be connected, but the loading time of the GIO line increases, resulting in deteriorated address access time
Solution Approach 1:
By segmenting the GIO line into multiple shorter lines (first GIO line for odd banks, second GIO line for even banks), the patent reduces the loading time for each segment while maintaining the ability to connect all banks, thus resolving the contradiction between bank connectivity and GIO line loading time.
3Adaptability or versatility
If the GIO line length is extended, then more banks can share the line, but a large amount of current is consumed to transfer data via the long GIO line
Solution Approach 1:
The patent segments the GIO line into multiple shorter lines, which reduces the current consumption for data transfer while maintaining the bank sharing capability. Each segment serves specific banks, allowing efficient current utilization without excessive consumption.
4Length of stationary object
If repeaters are added to separate core and Peri-area GIO lines, then the GIO line length is reduced, but the device complexity increases
Solution Approach 1:
The patent introduces repeaters that include delay units, transfer units, and buffer units to segment and manage the GIO lines. While this increases device complexity, it enables effective reduction of GIO line length and improvement of signal integrity, resolving the contradiction between GIO line length reduction and device complexity increase.
5Length of stationary object
If the GIO line length is reduced, then the chip size is minimized, but the number of necessary GIO lines increases
Solution Approach 1:
The patent segments the GIO line into multiple lines (first and second GIO lines) to reduce the length of each segment. Although this increases the number of GIO lines, it enables effective management of chip size and improvement of address access time characteristics, resolving the contradiction between GIO line length reduction and increase in the number of GIO lines.
Data Source
AI summary
A high-density semiconductor device includes a first input/output line connected among a plurality of banks on a core area storing data, so that it transmits data, a second input/output line connected to a data pad capable of performing data input/output operations at a Peri-area, so that it transmits data, a first repeater connected between the first input/output line and the second input/output line, for transmitting data of the first input/output line to the second input/output line in response to a read enable signal enabled by a read command, and a second repeater connected between the first input/output line and the second input/output line, for transmitting data of the second input/output line to the first input/output line in response to a write enable signal enabled by a write command.