DRAM Row Hammer Detection With Targeted Adjacent-Row Refresh
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Solution Overview
Problem
Existing DRAM systems face intermittent failures due to row hammering, which occurs from repetitive access to a single row causing parasitic electromagnetic coupling and data corruption in adjacent rows, and current methods to mitigate this issue require increasing the number of registers, which affects DRAM density.
Innovation Solution
A memory device with a row hammer managing circuit that detects row hammer addresses and performs refresh operations on adjacent rows using a reduced number of registers, employing a method that includes a first and second register to store and compare input addresses with a pre-determined row hammer address, and a refresh control circuit to perform targeted refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of registers is increased to monitor more row hammer addresses, then the ability to defend against various types of row hammer attacks is improved, but the DRAM density deteriorates
Solution Approach 1:
The patent divides the row hammer monitoring function into multiple stages: a monitoring circuit that detects frequently accessed row addresses, a determination circuit that identifies whether these addresses indicate row hammer attacks, and a refresh control circuit that performs targeted refresh operations. This segmentation allows the system to defend against various row hammer types without requiring a large number of registers, as each stage processes information sequentially rather than storing all possible row addresses simultaneously.
Solution Approach 2:
The patent implements a monitoring period during which row addresses are observed and counted before determining whether they represent row hammer attacks. This preliminary monitoring action allows the system to identify potential row hammer addresses without immediately committing register resources, enabling the system to adapt to different attack patterns while maintaining efficient resource utilization.
2Reliability
If the number of registers is increased to store more row hammer addresses, then the coverage of row hammer protection is improved, but the manufacturing complexity increases
Solution Approach 1:
The refresh control circuit is designed to perform multiple functions: it manages normal refresh operations, handles row hammer mitigation, and adapts to different types of row hammer attacks. By making this circuit universal, the patent eliminates the need for separate dedicated circuits for each row hammer type, thereby reducing the overall number of registers and simplifying the device architecture while maintaining comprehensive protection coverage.
Solution Approach 2:
The determination circuit automatically analyzes the monitored row addresses and determines whether they indicate row hammer attacks without requiring external intervention or configuration. This self-service capability allows the system to adapt to different attack patterns dynamically, reducing the need for pre-configured registers for each possible attack scenario.
3Productivity
If repetitive access to a single row is performed, then the row hammer effect is intensified, but data corruption in adjacent rows occurs
Solution Approach 1:
The patent implements a feedback mechanism where the monitoring circuit continuously observes row access patterns, the determination circuit analyzes whether these patterns indicate row hammer attacks, and the refresh control circuit responds by performing targeted refresh operations on affected rows. This closed-loop feedback system allows the memory device to detect and mitigate row hammer effects in real-time, preventing data corruption even under high access frequency conditions.
Solution Approach 2:
The system performs refresh operations on adjacent rows before data corruption can occur. By detecting repetitive access patterns early during the monitoring period and initiating refresh operations proactively, the system prevents the parasitic electromagnetic coupling from causing actual data corruption, thereby counteracting the harmful effects before they manifest.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively manages various types of row hammers without increasing register count, improving DRAM density and reliability by reducing the number of registers needed and enhancing integration.
Implementation Method 1
repeated accesses to a single row of memory cells, so-called row hammering. Repetitive access to a particular row may cause an increased rate of decay of adjacent rows (e.g., victim rows) due to parasitic electromagnetic coupling between the rows.
Data Source
AI summary
A memory device includes a memory cell array having a plurality of rows of memory cells therein, and a row hammer managing circuit, which is configured to detect a row hammer address based on a pre row hammer address, and each of a plurality of input row addresses associated with a plurality of accesses during a monitoring period for monitoring the plurality of accesses to a plurality of the rows of memory cells. A refresh control circuit is provided and is configured to perform a refresh operation on a memory cell row physically adjacent to a memory cell row corresponding to the row hammer address.