DRAM Row Hammer Counting With Targeted Adjacent-Row Refresh
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Solution Overview
Problem
Semiconductor memory devices, particularly DRAMs, face issues with data loss due to leakage currents and row hammer attacks, which degrade performance and increase power consumption, especially with increased memory capacity and manufacturing scale-down.
Innovation Solution
Incorporating a row hammer management circuit that automatically stores random count data during power-up, counts access frequencies, and identifies candidate hammer addresses to perform targeted refresh operations, reducing the need for external controller commands and managing row hammer attacks across all memory cell rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional refresh operations are performed frequently to prevent data loss from leakage current, then data retention reliability is improved, but power consumption increases
Solution Approach 1:
The patent applies preliminary action by proactively identifying rows susceptible to row hammer attacks through counting access patterns and storing this information in count cells before actual data loss occurs. The system performs refresh operations on predicted vulnerable rows rather than reacting after failures occur, enabling preventive maintenance that reduces overall refresh frequency and power consumption while maintaining reliability.
Solution Approach 2:
The memory device performs self-diagnosis and self-protection by autonomously counting access patterns, identifying vulnerable rows, and executing targeted refresh operations without external controller intervention. The row hammer management circuit automatically manages its own protection mechanisms, reducing the burden on external systems and enabling intelligent, adaptive refresh strategies that optimize power consumption.
2Measurement precision
If row hammer management is performed manually with external controller commands, then control precision is improved, but device complexity increases
Solution Approach 1:
The patent implements self-service by embedding the row hammer management functionality directly within the memory device. The row hammer management circuit autonomously counts access patterns, identifies vulnerable rows, and executes refresh operations without requiring continuous external controller commands. This integration maintains precise control while reducing overall system complexity by eliminating the need for complex external management infrastructure.
Solution Approach 2:
The patent introduces an intermediary structure (the row hammer management circuit with count cells) that mediates between the external controller and the memory array. This intermediary automatically handles the complex tasks of access pattern analysis and targeted refresh coordination, simplifying the interface with the external controller while maintaining precise management of row hammer effects.
3Reliability
If access counting and monitoring are performed continuously to identify hammer addresses, then attack detection capability is improved, but processing time increases
Solution Approach 1:
The patent applies preliminary action by continuously accumulating access count data in count cells during normal operation, so that when a row hammer attack is detected, the identification of vulnerable rows is already prepared. The system pre-processes access patterns and maintains sorted lists of vulnerable rows, enabling rapid response without real-time processing delays and reducing the time needed to execute protective refresh operations.
Data Source
AI summary
A semiconductor memory device includes a memory cell array, a row hammer management circuit and a refresh control circuit. The row hammer management circuit automatically stores random count data in count cells of each of a plurality of memory cell rows during a power-up sequence of the semiconductor memory device and determines counted values by counting a number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller and stores the counted values in the count cells of each of the plurality of memory cell rows as count data. The refresh control circuit receives a hammer address and performs a hammer refresh operation on one or more of the plurality of memory cell rows that are physically adjacent to a memory cell row that corresponds to the hammer address.