DRAM Vertical Transistor With Horizontal Body Contact for Off-Leakage
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Solution Overview
Problem
Current 4F2 DRAM devices experience off-leakage current issues due to the floating body effect caused by hole accumulation in vertical channel transistors, which degrades transistor performance.
Innovation Solution
A dynamic random-access memory transistor design featuring an in-situ doped polysilicon body contact formed between vertical pillars, with a bottom source/drain in the base layer and a top source/drain in each pillar, extending above the gate, which eliminates floating-body issues by providing a horizontal structure for hole/electron flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertical fin structures with high aspect ratio are used to scale DRAM devices, then device density is improved, but off-leakage current increases due to floating body effect
Solution Approach 1:
The patent extracts the body contact from the traditional vertical configuration and repositions it to a horizontal location between pillars. This removes the floating body effect by providing a dedicated path for hole extraction, while preserving the vertical fin structure for high device density.
Solution Approach 2:
The patent introduces a horizontal body contact as an intermediary structure between the vertical pillars and the substrate. This mediator provides a conductive path for hole extraction, resolving the floating body effect without compromising the vertical channel structure.
2Object-generated harmful factors
If horizontal body contact is introduced to eliminate floating body effect, then off-leakage current is reduced, but device structure complexity increases
Solution Approach 1:
The patent applies local quality by positioning the body contact only in specific regions between pillars where it is most needed for hole extraction, rather than implementing a comprehensive restructuring of the entire device. The spacer layer is also selectively positioned to facilitate this local modification.
Solution Approach 2:
The patent transitions from a purely vertical body contact configuration to a horizontal dimension, placing the body contact laterally between pillars. This dimensional change provides an effective hole extraction path while maintaining compatibility with the vertical fin structure.
3Ease of manufacture
If spacer layer is formed along lower portion of pillars, then body contact formation is simplified, but manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary action by forming the spacer layer on the lower portion of pillars before creating the body contact. This pre-positioned spacer layer serves as a template and protective layer that simplifies subsequent body contact formation and defines the contact region.
Solution Approach 2:
The patent segments the spacer layer formation to occur only on the lower portion of pillars rather than uniformly across all surfaces. This selective segmentation allows the spacer to serve its function of facilitating body contact formation without interfering with other device regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces contact resistance and improves transistor performance by allowing all S/D doping schemes, such as LDD and DSS, and eliminates floating-body issues, enhancing the overall performance of the DRAM device.
Implementation Method 1
a body contact and a cap between the plurality of pillars, wherein the body contact is formed over the spacer layer... providing a conductive path for holes and electrons
Implementation Method 2
etching a section of a spacer layer from an inner portion of each of a plurality of pillars by delivering ions to the spacer layer at a non-zero angle relative to a perpendicular extending from an upper surface of the plurality of pillars
Implementation Method 3
forming a bottom source/drain (S/D) in the base layer by delivering a dopant into the top surface of the base layer
Data Source
AI summary
Disclosed herein are approaches for forming a dynamic random-access memory device (DRAM). One DRAM device may include plurality of pillars extending from a base layer, and a spacer layer formed along just a lower portion of each of the plurality of pillars. The DRAM further includes a body contact and a cap between the plurality of pillars, wherein the body contact is formed over the spacer layer, and a gate formed around the plurality of pillars. The DRAM further includes a bottom source/drain formed in the base layer and a top source/drain formed in each pillar of the plurality of pillars, wherein the top source/drain extends above the gate.