DRAM IMC Accelerator With Dual-Mode Sensing and Compact MAC-SIMD
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Solution Overview
Problem
Current DRAM-based in-memory computing (IMC) technologies face challenges in memory density, high energy consumption during data read operations, limitations in achieving high energy efficiency while maintaining accuracy, limited functionality in supporting various AI operations, and restricted bit-serial bit-parallel data flow.
Innovation Solution
The IMC accelerator employs a high-density operation circuit with a 1T1C structure and a low-power sense amplifier, utilizing a dual mode sense amplifier and a big-little memory array, along with column addition data flow and signal enhancement operations to improve memory density, reduce energy consumption, and expand functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a DRAM cell is used for in-memory computing operations, then memory density is improved, but the operation cell area becomes 13 times larger than a DRAM cell and 36 times larger than an SRAM cell due to integration of additional transistors and capacitors
Solution Approach 1:
The patent merges memory and computation functions into a unified cell structure. The 1T1C cell integrates one transistor and one capacitor to perform both storage and in-memory computing operations (AND, OR, NOT, NAND, NOR, XOR), eliminating the need for separate operation circuits and reducing overall cell area.
Solution Approach 2:
The DRAM cell is designed to serve multiple functions: data storage, data processing, and logic operations. By enabling the cell to perform both memory and computing tasks, the patent achieves high memory density while keeping the operation cell area compact.
2Adaptability or versatility
If data is read using a sense amplifier and then operated in a peripheral circuit, then operation functionality is achieved, but consumed memory access energy becomes greater than or equal to operation energy due to driving the sense amplifier and changing bit line voltage
Solution Approach 1:
The patent combines the sense amplifier and operation circuit into a single integrated structure. The sense amplifier not only reads data from the memory array but also directly performs logical operations on the read data, eliminating the need for separate peripheral operation circuits and reducing energy consumption.
Solution Approach 2:
The sense amplifier acts as an intermediary that bridges memory reading and computation. Instead of reading data to a separate circuit for processing, the sense amplifier mediates by performing operations directly on the bit lines, reducing energy overhead.
3Adaptability or versatility
If half of a cell array is removed to integrate operators in a 1T1C cell, then in-memory operation capability is achieved, but high-density characteristics of DRAM cannot be utilized
Solution Approach 1:
The 1T1C cell structure enables each cell to function as both a memory element and a logic gate. By making the cell universal, the patent maintains the full cell array without removal, preserving high memory density while enabling in-memory computing operations.
4Productivity
If conventional analog IMC technology uses bit-serial bit-parallel data flow, then MAC operations are performed, but energy efficiency is limited by repeatedly requiring ADC operation and digital accumulation for each single input bit
Solution Approach 1:
The patent extracts the ADC operation from the processing pipeline and eliminates it entirely. By performing all operations in the analog domain using voltage levels directly, the system removes the energy-consuming ADC conversion step that is required in conventional approaches.
Solution Approach 2:
The patent replaces the mechanical/conversion-based ADC operation with direct analog voltage processing. Instead of converting analog voltages to digital values, the system performs logical operations directly on analog voltage levels, significantly reducing energy consumption.
Data Source
AI summary
An in-memory computing (IMC) accelerator using a high-density operation circuit and a low-power sense amplifier as a peripheral circuit includes a plurality of dynamic random-access memory (DRAM) banks each including a pair of cell arrays, a data supply logic, a memory, and a controller for IMC, a global SRAM, and a top-level controller, wherein the cell array includes a plurality of subarrays, each of the subarrays includes a DRAM array including a big array and a little array, and an arithmetic circuit configured to perform an operation, and the arithmetic circuit includes a sense amplifier configured to amplify a bit line voltage difference, and a compact multiply-accumulate (MAC)-single instruction multiple data (SIMD) unit (CMSU) for an MAC operation and an SIMD operation, so that functionality of an in-memory operation is diversified.