DRAM Interface Circuit Layout for Data-Clock Timing Matching
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Solution Overview
Problem
The mismatch in timing between data and clock paths in DRAMs, particularly in LPDDR4 and LPDDR5, leads to timing violations and increased power consumption due to varying lengths of data and clock paths affecting tDQS2DQ and tWCK2DQ, which are critical for proper data transmission.
Innovation Solution
The interface circuit design centrally arranges input buffer circuits relative to the clock pad, reducing the clock path lengths and improving the matching of data and clock paths by minimizing the distance between input buffer circuits and the central axis, thereby reducing tDQS2DQ and tWCK2DQ, and optimizing the layout to enhance timing consistency and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data pads are arranged in a conventional layout, then the interface circuit can transmit data signals, but the clock path length varies significantly for different input buffer circuits, causing timing mismatches
Solution Approach 1:
The patent applies asymmetry by arranging input buffer circuits at different distances from the clock pad based on their position in the array. Specifically, input buffer circuits on one side of the clock pad are positioned closer than those on the other side, creating intentional asymmetric path length differences that are then compensated through delay adjustment to achieve uniform effective timing
Solution Approach 2:
The patent implements local quality by assigning different delay characteristics to different input buffer circuits based on their specific positions relative to the clock pad. Each input buffer circuit receives a customized delay adjustment tailored to its local timing requirements, rather than applying a uniform delay to all circuits
2Productivity
If input buffer circuits are positioned far from the clock pad, then more data pads can be accommodated, but the clock path length increases causing timing violations
Solution Approach 1:
The patent applies preliminary action by pre-calculating and pre-adjusting the delay characteristics of each input buffer circuit during the design and fabrication process. The delay adjustment is built into the circuit before operation, allowing the system to achieve accurate timing without requiring real-time adjustment during data transmission
Solution Approach 2:
The patent implements parameter changes by modifying the delay parameter of each input buffer circuit individually. The delay characteristic is adjusted as a controllable parameter to compensate for variations in clock path length, enabling the system to maintain timing accuracy despite different physical distances from the clock pad
3Ease of manufacture
If unequal path lengths are used for different input buffer circuits, then layout flexibility is improved, but timing mismatches occur requiring additional delay adjustment circuits
Solution Approach 1:
The patent applies segmentation by dividing the clock distribution system into multiple independent segments, each serving a specific input buffer circuit. This allows each segment to be optimized independently with its own delay characteristics, enabling flexible layout while maintaining timing accuracy through localized adjustment
Data Source
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AI summary
Embodiments of the disclosure relate to the technical field of semiconductors, and disclose an interface circuit, a data transmission circuit and a memory. The interface circuit includes a clock pad (102), data pads (101) and input buffer circuits (103), where the clock pad (102) and the data pads (101) are arranged in the first row, and the M data pads (101) are arranged on two sides of the clock pad (102), half of the M data pads (101) being arranged on each side, where the M input buffer circuits (103) are arranged in the second row and form an axis (AA1) perpendicular to the first row with the data pads (102) as reference, and the M input buffer circuits (103) are arranged on two sides of the axis (AA1), half of the M input buffer circuits (103) being arranged on each side, and where the distance between each input buffer circuit (103) and the axis (AA1) is smaller than the distance between the data pad (101) corresponding to the input buffer circuit (103) and the axis AA1.