DRAM Isolation Gaps in 4F2 GAA Arrays to Reduce Parasitic Capacitance
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Solution Overview
Problem
Existing dynamic random access memories (DRAMs) with 4F2 GAA structures face increased parasitic capacitance due to reduced distances between channel pillars, affecting device performance.
Innovation Solution
A semiconductor structure with channel pillars, BLs, and WLs arranged perpendicularly, featuring insulating material layers with strategically formed gaps between adjacent BLs, around pillars below BLs, and between WLs to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the distance between channel pillars is reduced to increase storage density, then the area and storage density are improved, but parasitic capacitance between conductive materials increases and affects device performance
Solution Approach 1:
The patent extracts the harmful insulating material from between the bit lines to create gaps. This removal eliminates the source of parasitic capacitance while preserving the beneficial insulation elsewhere. The insulating material is selectively taken out from specific regions where it causes harm (between BLs) while maintaining it in regions where it provides necessary isolation.
Solution Approach 2:
The patent applies different insulation qualities to different spatial locations. Gaps are created only in specific regions between bit lines where parasitic capacitance is problematic, while insulating material is maintained in other regions for necessary electrical isolation. This local differentiation of insulation quality reduces parasitic capacitance without compromising overall device isolation requirements.
2Reliability
If insulating material layers are formed completely around channel pillars for isolation, then electrical isolation is improved, but parasitic capacitance between adjacent conductive structures increases
Solution Approach 1:
The patent selectively removes insulating material from regions between bit lines to eliminate parasitic capacitance sources. This extraction creates gaps that reduce capacitive coupling while the insulating material is retained in other critical isolation regions, maintaining necessary electrical isolation between different conductive elements.
Solution Approach 2:
The patent segments the insulating material distribution into distinct regions: gaps are created in specific areas between bit lines where isolation is less critical, while insulating material is maintained in other regions for essential electrical separation. This spatial segmentation allows differential insulation strategies to address both isolation and parasitic capacitance concerns.
Data Source
AI summary
The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base; a plurality of channel pillars perpendicularly provided on the base; a plurality of parallel bit lines, each of the bit lines wrapping lower parts of one column of the channel pillars; and a plurality of parallel word lines, each of the word lines wrapping upper parts of one row of the channel pillars, where the word lines and the bit lines are perpendicular to each other on a same projection plane; an insulating material layer is formed around the channel pillars below the bit lines, between adjacent bit lines, around the channel pillars between the bit lines and the word lines, and between adjacent word lines, separately; and gaps are formed in at least one of the insulating material layers.