DRAM Isolation Wall Doping for Void-Free Capacitor Contact Holes
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Solution Overview
Problem
As semiconductor manufacturing miniaturizes, the high aspect ratio of capacitor contact holes in DRAM structures leads to voids during filling, increasing wire resistance and parasitic capacitance due to the challenges in filling and the properties of existing isolation layers.
Innovation Solution
The semiconductor structure incorporates a dual-layer isolation system where the second isolation part, doped with ions, has a higher hardness or lower dielectric constant than the first part, reducing the number of isolation layers and total thickness, thereby increasing the bottom area of capacitor contact holes and reducing resistance and parasitic capacitance, and ensuring complete filling without voids or oxide layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the capacitor contact hole size is miniaturized to accommodate smaller DRAM structures, then the integration density is improved, but the aspect ratio increases and voids occur during filling
Solution Approach 1:
The isolation layer is divided into two distinct parts: a first isolation part adjacent to the bit line structure and a second isolation part deviating from it. This segmentation allows each part to have optimized properties for its specific function, with the second part having higher hardness to prevent void formation during filling of the miniaturized capacitor contact hole.
Solution Approach 2:
Different regions of the isolation layer are given different material properties. The second isolation part has higher hardness than the first isolation part, creating local quality variation that specifically addresses the void formation problem in the capacitor contact hole region while maintaining other necessary properties in adjacent regions.
2Device complexity
If conventional isolation layers are used, then the manufacturing process is simple, but the wire resistance and parasitic capacitance increase due to voids
Solution Approach 1:
The hardness parameter of the isolation layer is changed in the second isolation part through ion doping or material selection. This parameter change increases the hardness to prevent void formation during filling, thereby improving the reliability of the conductive plug without significantly complicating the overall device structure.
3Device complexity
If the isolation layer has uniform properties, then the manufacturing process is simplified, but the process window for capacitor contact hole formation is reduced
Solution Approach 1:
The isolation layer transitions from uniform to non-uniform with distinct first and second parts having different properties. The second isolation part with higher hardness provides a larger process window for capacitor contact hole formation and filling, while the first isolation part maintains other necessary properties for device operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the resistance of conductive plugs and parasitic capacitance, prevents voids and oxide formation, and enlarges the process window for capacitor contact holes, ensuring effective material deposition and improved conductive performance.
Implementation Method 1
doped ions are provided in the second isolation part of the at least one of the isolation layer
Implementation Method 2
a dielectric constant of the second isolation part is less than that of the first isolation part
Data Source
AI summary
A semiconductor structure includes: a substrate with conductive contact regions; a bit line structure and an isolation wall located on a sidewall of the bit line structure, the isolation wall includes at least one isolation layer including a first isolation part close to the bit line structure and a second isolation part deviating from the same, the second isolation part has doped ions, such that it has a greater hardness than the first isolation part, or has a smaller dielectric constant than the first isolation part; and a capacitor contact hole, which exposes the conductive contact region, and has a top width greater than a bottom width in a direction parallel to an orientation of the bit line structure.