DRAM L2P Address Table Layout for Compressed Physical Address Packing
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Solution Overview
Problem
Existing SSDs face challenges in managing address indirection tables, where long physical addresses cause issues in accessing and storage, and more bits are needed to efficiently pack physical addresses, and more bits are needed to efficiently pack physical address tables.
Innovation Solution
The implementation of a method is to store physical addresses in a DRAM or NAND memory system, where the method includes storing physical address data efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If physical addresses are stored using more bits to represent unique locations in larger capacity memory systems, then the address indirection table can accommodate more physical address locations, but the storage space required for the table increases and access time increases
Solution Approach 1:
The patent segments physical addresses into multiple fields within a compressed format. Instead of storing complete N-bit physical addresses (where N>32), the system divides addresses into segment identifiers and offset components, storing only the necessary segments in the address indirection table. This segmentation allows the table to accommodate larger address spaces while reducing the storage space required for each address entry.
Solution Approach 2:
The patent implements a nested address structure where compressed address entries in the indirection table contain segment identifiers that reference larger address spaces. The compressed format nests multiple levels of address information, allowing the system to represent N-bit physical addresses using fewer bits in the table by leveraging hierarchical address decomposition.
2Adaptability or versatility
If physical addresses are made longer to address more memory units, then more memory locations can be addressed, but the access time within burst length increases and power consumption increases
Solution Approach 1:
The patent extracts only the essential segments of physical addresses needed for indirection table operations. By taking out and storing only the critical address segments (而非 complete N-bit addresses), the system reduces the time required to read and process address information while still maintaining the ability to address large memory spaces through the compressed format.
Solution Approach 2:
The patent changes the parameter representation of physical addresses from full N-bit width to a compressed format with fewer bits. This parameter transformation maintains the addressing capability for large memory spaces while reducing the time and power required for address access operations in the indirection table.
3Adaptability or versatility
If more bits are used to represent each physical address in the address indirection table, then more unique physical address locations can be represented, but the storage efficiency decreases and space is wasted
Solution Approach 1:
The patent implements a dynamic address compression scheme where the number of bits used to represent physical addresses in the indirection table varies based on the actual address space requirements. Instead of allocating fixed N-bit fields for all addresses, the system dynamically adjusts the compressed format to use only the necessary bits, eliminating wasted space while maintaining adaptability to different address space sizes.
Data Source
AI summary
This application is directed to compressing a logical-to-physical address indirection table in a memory system of an electronic device. The electronic device identifies an address block including a plurality of physical addresses that corresponds to an ordered sequence of logical addresses. Each logical address corresponds to a distinct physical address. The electronic device further determines that a first physical address is associated with a first word having a first word location in the address block, and extracts the first word from the first word location in the address block. Based on the first word location, the electronic device determines a first bit location in a supplemental word that is distinct from the first word. The electronic device extracts at least a first bit from the first bit location of the supplemental word, and generates the first physical address based on the first word and the first bit.