Laminated Bit Line Contact Layout for Low-Resistance DRAM Cells
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Solution Overview
Problem
In the development of dynamic random access memory (DRAM), it is challenging to optimize the resistor-capacitance characteristics of the bit line contact structure, particularly in reducing contact resistance, which hinders the improvement of electrical performance as semiconductor technology advances into the deep submicron phase.
Innovation Solution
A semiconductor structure and manufacturing method involving a substrate with a shallow trench isolation (STI) structure and laminated contact structures, where the first contact structure covers part of the top surface and side wall of the active structure, and the second contact structure further covers the first contact structure, effectively reducing contact resistance while maintaining minimal critical dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the line width in DRAM is reduced to enter deep submicron phase, then the design size is improved, but the contact resistance of bit line contact structure increases
Solution Approach 1:
The contact structure transitions from a planar configuration to a three-dimensional laminated structure that wraps around the active structure. The first contact structure covers the top surface while the second contact structure covers the side wall, effectively adding a vertical dimension to the contact area. This dimensional transition increases the contact area without increasing the lateral footprint, thereby reducing contact resistance despite reduced line width.
Solution Approach 2:
The laminated contact structure implements a nested configuration where the second contact structure is positioned on the side wall of the active structure, and the first contact structure is positioned on the top surface. This nested arrangement maximizes the contact area within the constrained lateral dimensions, allowing the contact structure to effectively 'wrap around' the active structure and reduce resistance without increasing overall device size.
2Reliability
If the contact area is increased to reduce contact resistance, then the electrical performance is improved, but the device area increases
Solution Approach 1:
Instead of increasing contact area in the lateral plane, the invention utilizes the vertical dimension by creating a laminated structure that wraps around the active structure. The first contact structure extends in one lateral direction while the second contact structure extends in a perpendicular lateral direction, effectively using three-dimensional space to increase contact area without increasing the device's lateral footprint.
Solution Approach 2:
The contact structure applies local quality enhancement by concentrating the contact area increase at specific locations around the active structure. The laminated configuration ensures that the increased contact area is localized to where it is most effective (top surface and side wall), rather than uniformly distributing material throughout the device, thereby improving resistance without proportionally increasing overall device area.
Data Source
AI summary
The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate and a contact structure. The substrate includes a shallow trench isolation (STI) structure and active structures separated by the STI structure. The contact structure includes a first contact structure and a second contact structure that are laminated, where the first contact structure covers a part of a top surface and a part of a side wall of the active structure.