DRAM LIDAR Pixel Histogramming With Low-Transistor Memory Bins
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Solution Overview
Problem
Conventional LIDAR systems face inefficiencies in memory resource utilization due to sparse occupancy of histogram bins in time-of-flight measurements, leading to increased complexity and power requirements in SRAM-based detector pixels, particularly in applications requiring high sensitivity and timing resolution.
Innovation Solution
The implementation of a DRAM-based memory system with a control circuit that performs increment and refresh operations within the time between emitter signal pulses, utilizing fewer transistors and allowing for sequential memory access, thereby reducing power consumption and increasing memory density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If SRAM-based memory is used in LIDAR detector pixels, then memory speed and access time are improved, but device complexity and transistor count increase significantly
Solution Approach 1:
The patent extracts the memory function from traditional SRAM-based detector pixels and implements it using DRAM technology instead. This separation allows the detector pixel to use fewer transistors while maintaining memory functionality through the DRAM-based time-to-digital converter that performs histogramming operations externally.
Solution Approach 2:
The patent replaces the mechanical/electrical SRAM memory structure with a DRAM-based system that uses capacitive storage and refresh operations. This substitution reduces the transistor count from 32+ transistors per bit in SRAM to significantly fewer transistors in DRAM, while maintaining the necessary memory functionality for time-of-flight measurements.
2Measurement precision
If deeper memory depth is implemented to cover maximum expected laser returns, then measurement dynamic range is improved, but memory resource utilization deteriorates due to sparse occupancy
Solution Approach 1:
The patent implements dynamic memory allocation where the histogram bin depth and number of bins can be adjusted based on the actual measurement requirements. The DRAM-based TDC allows flexible reconfiguration of memory resources to match the expected photon return distribution, optimizing both dynamic range and resource utilization.
Solution Approach 2:
The patent changes the memory organization parameters from fixed SRAM structures to configurable DRAM structures. The time-to-digital converter uses DRAM with adjustable bin depths and refresh rates that can be optimized for different measurement scenarios, allowing the system to adapt to varying dynamic range requirements without over-provisioning memory resources.
3Measurement precision
If more time bins are used to increase TDC resolution, then time measurement precision is improved, but memory resources increase and refresh operations become more frequent
Solution Approach 1:
The patent uses periodic refresh operations on the DRAM-based histogram bins to maintain data integrity. The refresh rate is optimized to match the laser pulse repetition frequency, allowing the system to use fewer time bins while maintaining effective time resolution through the periodic nature of the measurements and refresh cycles.
Solution Approach 2:
The patent maintains continuous accumulation of photon arrival times in the DRAM histogram bins across multiple laser pulses. The memory continuously updates the time-of-flight distribution, allowing high time resolution to be achieved through statistical accumulation rather than requiring excessively fine time binning, thereby reducing the total number of memory resources needed.
4Device complexity
If DRAM-based memory is used to reduce transistor count, then device complexity is reduced, but reliability deteriorates due to bit leakage issues
Solution Approach 1:
The patent performs preliminary refresh operations on the DRAM cells before they lose their stored data. The control circuit monitors and refreshes the histogram bin data at intervals that prevent bit leakage, ensuring data integrity is maintained throughout the measurement period while using the lower-complexity DRAM structure.
Solution Approach 2:
The patent implements feedback control where the system monitors the charge retention in DRAM cells and adjusts the refresh timing accordingly. This feedback mechanism ensures that data is refreshed before significant leakage occurs, maintaining reliability while benefiting from the reduced transistor count of DRAM technology.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more compact and efficient memory operations, improving the resolution and dynamic range of LIDAR systems by reducing the number of transistors per pixel and optimizing memory refresh rates, which helps in overcoming bit leakage issues and enhancing the accuracy of time-of-flight measurements.
Implementation Method 1
The initiating charge carrier can be photo-electrically generated by a single incident photon striking the high field region
Implementation Method 2
The high reverse bias voltage generates a sufficient magnitude of electric field such that a single charge carrier introduced into the depletion layer of the device can cause a self-sustaining avalanche via impact ionization
Implementation Method 3
A memory device, such as Static Random Access Memory (SRAM), may be used for memory storage
Data Source
AI summary
A Light Detection and Ranging (LIDAR) detector circuit includes a memory device comprising a non-transitory storage medium that is configured to store data indicative of detection events in respective memory bins, and at least one control circuit. The at least one control circuit is configured to receive detection signals from one or more photodetector elements, identify a presence or an absence of detection events indicated by the detection signals during a portion of time between pulses of an emitter signal output from a LIDAR emitter element, and execute one of a first memory operation or a second memory operation to update the data in the respective memory bins responsive to identification of the presence or the absence of the detection events, respectively. Related circuits and methods of operation are also discussed.