DRAM Bit Line Liner Structure to Prevent Capacitor Contact Shorts
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Solution Overview
Problem
As DRAM elements shrink, the self-align etching process leads to difficulties in cleaning materials in corners, causing capacitor contacts to short-circuit, necessitating improved fabrication methods to enhance DRAM performance and density.
Innovation Solution
A semiconductor memory structure is developed with a dielectric liner comprising multiple nitride and oxide layers, where a portion of the dielectric material layer and nitride liners are removed to increase the distance between capacitor contacts, preventing short-circuits by forming a filler with a rounded corner that maintains the same width as the bit lines, thereby avoiding direct contact with the capacitor contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If elements are scaled down to increase density, then DRAM density and overall performance are improved, but materials in corners become hard to clean and capacitor contacts are prone to short-circuiting
Solution Approach 1:
The patent extracts and removes the dielectric material layer and portion of the nitride liner from the corner regions, creating a rounded corner profile. This extraction eliminates the material accumulation that causes short-circuiting in scaled-down devices, thereby maintaining reliability while preserving density improvements.
Solution Approach 2:
The patent introduces curvature by rounding the corners of the capacitor contact opening. Instead of sharp 90-degree corners that trap materials, the rounded corner profile allows for complete material removal and prevents material accumulation, solving the short-circuit problem in scaled devices.
2Ease of manufacture
If a simple dielectric liner is used, then manufacturing process is simpler, but capacitor contacts are prone to short-circuiting in corners
Solution Approach 1:
The dielectric liner is segmented into multiple functional layers: a first nitride liner layer, an oxide liner layer, and a second nitride liner layer. Each layer serves a specific purpose in preventing short-circuits during the scaling process while maintaining overall process feasibility.
Solution Approach 2:
The patent uses a composite dielectric liner structure combining different materials (nitride and oxide layers) with distinct properties. This composite structure provides both the mechanical support needed for scaling and the chemical properties required to prevent material accumulation and short-circuiting.
3Reliability
If distance between capacitor contacts is increased, then short-circuiting is prevented, but device density decreases
Solution Approach 1:
The patent applies local quality by modifying only the corner regions where short-circuiting occurs, rather than increasing the overall distance between capacitor contacts. The rounded corner profile locally increases spacing at critical points while maintaining tight pitch elsewhere, preserving device density.
Data Source
AI summary
A semiconductor memory structure includes a substrate, a bit line disposed on the substrate, a dielectric liner disposed on a side of the bit line, and a capacitor contact and a filler disposed on the substrate. The bit line extends in a first direction. The dielectric liner includes a first nitride liner disposed on a sidewall of the bit line, an oxide liner disposed on a sidewall of the first nitride liner, and a second nitride liner disposed on a sidewall of the oxide liner. In a second direction perpendicular to the first direction, the capacitor contact is spaced apart from the bit line by the first nitride liner, the oxide liner, and the second nitride liner, and the width of the filler is greater than the width of the capacitor contact. A method for forming the semiconductor memory structure is also provided.