Low-k Word Line Capping Structure for DRAM Parasitic Capacitance

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Solution Overview

Problem

As the integration of memory devices increases, parasitic capacitance and leakage current degrade the performance of dynamic random access memory (DRAM) devices, particularly affecting signal margin due to charge sharing effects.

Innovation Solution

A memory structure is designed with a low dielectric constant material used for the capping layer of the word line structure, which reduces bit-line parasitic capacitance and gate-induced drain leakage (GIDL) current, thereby enhancing signal margin.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If integration of memory device is increased, then memory density is improved, but parasitic capacitance and leakage current increase degrading performance

Engineering Contradiction:

Improvememory densityVSAvoidparasitic capacitance and leakage current

Core Design Contradiction:

Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

The patent changes the dielectric constant parameter of the capping layer material from conventional high-k material to low-k material (with dielectric constant less than that of silicon nitride), which directly reduces parasitic capacitance and GIDL current while maintaining high memory density

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent uses composite material structure with word line including first layer (metal, e.g., tungsten) and second layer (semiconductor, e.g., polysilicon), combined with low-k capping layer material, to achieve both high density and reduced parasitic effects

Inventive Principle:

Principle #40Composite materials

2Ease of manufacture

If conventional capping layer material (silicon nitride or higher dielectric constant) is used, then manufacturing is simplified, but bit line parasitic capacitance increases reducing signal margin

Engineering Contradiction:

Improvemanufacturing simplicityVSAvoidbit line parasitic capacitance

Core Design Contradiction:

Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The implementation of a low dielectric constant capping layer effectively reduces parasitic capacitance and leakage current, leading to an increased signal margin and improved performance of the memory structure during operation.

Implementation Method 1

The capping layer includes a first material film, and a dielectric constant of the first material film is smaller than a dielectric constant of silicon nitride

Methodology Applied

Scientific EffectDielectric constant: Dielectric Permittivity

Data Source

PatentUS12328868B2Memory structure including low dielectric constant capping layer

Publication Date: 2025.06.10 NAN YA TECH

AI summary

A memory structure is described, which includes a substrate, a word line structure, a bit line contact, and a bit line. The substrate has a trench. The word line structure is disposed in the trench of the substrate. The word line structure includes a word line, a gate dielectric layer, and a capping layer. The word line is disposed in the trench. The gate dielectric layer is disposed between the word line and the substrate. The capping layer covers the word line. The capping layer includes a first material film, and a dielectric constant of the first material layer is smaller than a dielectric constant of silicon nitride. The bit line contact is disposed on a portion of the trench and a portion of the capping layer. The bit line is disposed over the bit line contact and electrically connected to the bit line contact.