In-DRAM Max/Min Search Using Single-Cycle XNOR Logic
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Solution Overview
Problem
Conventional computer systems face challenges in implementing fast and efficient min/max searching for big data due to memory architecture limitations and computing algorithm constraints, particularly in in-DRAM computing platforms which lack full system compatibility and are power-intensive for X(N)OR logic operations.
Innovation Solution
A method and system for calculating minimum or maximum values in volatile memory using bitwise XNOR operations, optimized for in-memory applications, which initializes comparison vectors, performs transposed copying, and iteratively updates matching vectors to identify boundary values within a single clock cycle, leveraging combinatorial logic gates and a processor integrated on a single printed circuit board or integrated circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If in-DRAM computing platforms use charge sharing-based majority gates for XNOR logic, then min/max searching functionality is provided, but multiple cycles are required and power consumption increases due to intermediate data writeback
Solution Approach 1:
The patent replaces the traditional charge sharing-based majority gate mechanism with a novel in-DRAM logic circuit that performs XNOR operations. This substitution eliminates the need for multiple computation cycles and intermediate data writeback operations, achieving single-cycle XNOR logic while reducing power consumption. The new mechanism uses voltage threshold comparisons and charge state detection to directly determine logical results without mechanical charge sharing steps.
Solution Approach 2:
The patent extracts and removes the intermediate data writeback step from the computation process. By directly computing XNOR results within the DRAM array without writing intermediate results back to memory, the system eliminates unnecessary memory access cycles and reduces overall computation time while maintaining functional correctness.
2Adaptability or versatility
If conventional computer systems use CPU/GPU for min/max searching, then complex computing instructions are supported, but off-chip data transfer power consumption is two-orders higher than data processing
Solution Approach 1:
The patent merges the data storage function and data processing function into a single integrated system within the DRAM array. By combining memory cells with logic circuitry to perform XNOR operations directly on stored data, the system eliminates separate data transfer between memory and processor, thereby reducing power consumption associated with off-chip data movement while maintaining computational capability.
Solution Approach 2:
The patent introduces an intermediary in-DRAM logic circuit that acts as a bridge between stored data and computation results. This intermediary performs processing operations directly within the memory array, eliminating the need for data to travel to external processors and reducing the energy cost of data transfer while still supporting complex computing operations.
3Adaptability or versatility
If in-DRAM computing platforms perform XNOR logic with multiple cycles, then complete Boolean logic operations are achieved, but system compatibility is limited and computation speed decreases
Solution Approach 1:
The patent replaces the multi-cycle charge sharing mechanism with a direct voltage threshold comparison mechanism that achieves complete Boolean logic operations in a single cycle. The new system uses threshold voltage comparisons and charge state detection to fully evaluate logical conditions without requiring multiple sequential steps, thereby maintaining logical completeness while dramatically improving computation speed.
Solution Approach 2:
The patent performs preliminary setup of voltage thresholds and charge states before the actual XNOR operation. By pre-configuring the logic circuit with appropriate reference voltages and initial charge conditions, the system enables single-cycle completion of Boolean logic operations without requiring multiple iterative cycles to establish the logical state.
Data Source
AI summary
A method of calculating a boundary value of a set of numerical values in a volatile memory comprises storing a set of numerical values in a volatile memory, initializing a comparison vector, initializing a matching vector, transpose-copying a first bit of each of the set of numerical values into a buffer, calculating a result vector, updating the matching vector, repeating the previous steps for each of the bits in the set of numerical values, and returning the matching vector, where the position of each 1 remaining in the matching vector corresponds to an index of the boundary value in the set of numerical values, wherein the computation and the memory storage take place on the same integrated circuit. A system for calculating a boundary value of a set of numerical values is also disclosed.