DRAM Semiconductor Memory for Low-Power Multiply-Accumulate
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Solution Overview
Problem
Existing semiconductor memories face challenges in performing high-speed multiply-accumulate operations for machine learning due to limitations in access speed, power consumption, and the ability to handle increasing dimensions of data sets, particularly when using nonvolatile memories like NAND flash.
Innovation Solution
Utilizing dynamic random access memory (DRAM) for CIM calculations, which allows for easy handling of negative numbers and supports a larger number of dimensions without increasing power consumption, by employing memory cell groups with complementary data storage and switches to manage data rewriting during calculations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the configuration size of the CIM is increased to handle higher dimensional data sets, then the quality of machine learning is improved, but the power consumption increases
Solution Approach 1:
The memory array is divided into multiple memory cell groups (e.g., 32 groups) that can be independently activated. Only the necessary memory cell groups corresponding to the actual data dimensionality are activated for each calculation task, rather than activating the entire memory array. This segmentation allows the system to handle variable dimensionalities efficiently while maintaining low power consumption by keeping unused segments in a low-power state.
2Adaptability or versatility
If the circuit size of the CIM is increased to accommodate more dimensions, then the data processing capability is improved, but the access speed and reliability are affected
Solution Approach 1:
The memory array is divided into multiple memory cell groups (e.g., 32 groups) that can be independently activated. Only the necessary memory cell groups corresponding to the actual data dimensionality are activated for each calculation task, rather than activating the entire memory array. This segmentation allows the system to handle variable dimensionalities efficiently while maintaining low power consumption by keeping unused segments in a low-power state.
Solution Approach 2:
Complementary data is pre-stored in adjacent memory cells before calculations are performed. This preliminary preparation of data in complementary form eliminates the need for complex real-time computations during the calculation phase, enabling faster access and processing speeds while maintaining the ability to handle high-dimensional data sets.
3Stability of the object's composition
If nonvolatile memory is used for CIM calculations, then data retention is improved, but the access speed and ability to handle negative numbers are limited
Solution Approach 1:
The patent replaces nonvolatile memory (which has slow access speed and limited capability for handling negative numbers) with DRAM technology. DRAM provides significantly faster access speeds and naturally supports bipolar values (positive and negative numbers) through its charge-based storage mechanism, while still maintaining sufficient data retention for the duration of CIM calculations through its volatile but fast-access nature.
Data Source
AI summary
A semiconductor memory includes memory cell groups storing first data; pairs of first wiring lines transmitting second data including bits; second wiring lines transmitting a signal corresponding to a product of one bit of the first data and a corresponding bit of the second data; sense amplifiers sensing the signal corresponding to the product transmitted from the second wiring lines; a third wiring line transmitting a signal corresponding to a value adding the products; and switches disposed between the second wiring lines and the third wiring line, each being in an off state in order to disconnect the second wiring lines and the third wiring line until data read to the second wiring lines from the memory cell groups and sensed by the sense amplifiers is rewritten to the memory cell groups, and turned on to connect the second wiring lines and the third wiring line.