DRAM Memory Routing Module for Smaller Processor IO Footprint
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Solution Overview
Problem
Current high-performance computing systems face challenges in achieving high-capacity memory access and efficient processor communication due to the significant area consumed by beachfront IO circuits, limiting the processing core area and increasing costs.
Innovation Solution
A memory and routing module comprising a substrate with DRAM chips, routing chips, and connection components that allow processor chips to communicate through fabric chips, reducing the need for direct processor-to-processor connections and enabling all-to-all bipartite connectivity with external memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If beachfront IO circuits are used to connect processors to external memory and enable inter-processor communication, then memory access and processor communication are enabled, but the processing core area is significantly reduced and manufacturing costs increase
Solution Approach 1:
The system divides the cluster into multiple processing nodes, each with its own local memory and IO circuits. By segmenting the memory and IO functions across multiple nodes rather than requiring all processors to share a common beachfront area, each processor can have a smaller core area while maintaining access to high-capacity memory through its dedicated memory controller and memory interface circuits.
Solution Approach 2:
Memory controllers act as intermediary components between processors and external memory. The memory controller handles memory access requests, freeing processors from direct memory interface requirements and reducing the beachfront area needed for memory connectivity. The memory controller serves as a mediator that manages the interface between the processor core and external memory resources.
2Ease of manufacture
If beachfront area is reduced to maximize processing core area, then manufacturing costs are reduced, but the ability to connect to high-capacity external memory and enable inter-processor communication is compromised
Solution Approach 1:
The memory controller is designed to perform multiple functions: it manages external memory access, handles inter-processor communication routing, and coordinates data flow between processors and memory. This multi-functionality allows the system to maintain high-capacity memory connectivity and inter-processor communication capabilities while using fewer dedicated IO circuits, thereby reducing beachfront area and manufacturing costs.
Solution Approach 2:
The system changes the architectural parameters by moving memory controllers and memory interface circuits outside the processor core area and into dedicated memory modules. This parameter change allows the processor to have a smaller, more cost-effective beachfront area while still maintaining access to high-capacity external memory through the external memory interface and memory controller.
3Speed
If direct processor-to-processor connections are implemented for inter-processor communication, then communication speed is improved, but the beachfront area required increases and processing core area decreases
Solution Approach 1:
The memory controller and routing logic serve as intermediary components that enable fast inter-processor communication without requiring direct processor-to-processor connections. Data can be rapidly transferred between processors by routing through the memory controller and memory interface, maintaining high communication speed while reducing the beachfront area needed for direct inter-processor links.
Data Source
AI summary
A memory and routing module includes a substrate and a connection component. The connection component is attached to the substrate and includes multiple pins that connect the module to a corresponding connection component on a motherboard. The substrate is connected to a dynamic random-access memory, DRAM, chip, and a routing chip. The routing chip includes a memory controller, multiple connections, and routing logic. The multiple connections include a first group between the memory controller and the DRAM chip and a second group of connections with the pins of the connection component. The routing logic routes data between the second group of connections and the first group of connections.