DRAM Data Output Clock Control for Narrow Read Pulses
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Solution Overview
Problem
Conventional semiconductor memory devices fail to generate clock signals necessary for data output when the pulse width of the internal clock is narrow, leading to incomplete data output in DRAM.
Innovation Solution
A data output controller is designed with an enable signal controller and clock generator that synchronize the clock enable signal with a control signal generated from a DQ off signal, write signal, and read signal, ensuring the generation of data clock signals even with varying internal clock pulse widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the read signal has a narrow pulse width, then the operation speed is improved, but the clock enable signal cannot be maintained at a low level, resulting in failure to generate data clocks
Solution Approach 1:
The control signal generator pre-generates a control signal with a predetermined pulse width that is wider than the minimum required read signal pulse width. This preliminary action ensures that even when the read signal has a narrow pulse width for high-speed operation, the control signal maintains sufficient duration to properly generate the clock enable signal and subsequent data clocks, thus preventing data output failure.
2Adaptability or versatility
If the internal clock pulse width is changed, then the clocking flexibility is improved, but the synchronization between read signal and Node B signal cannot be maintained, causing data output failure
Solution Approach 1:
The control signal acts as an intermediary between the read signal and the clock generation process. The control signal generator receives the read signal and generates a control signal with a predetermined pulse width that is independent of the internal clock pulse width variations. This intermediary control signal then synchronizes the clock enable signal generation, ensuring stable data output even when internal clock pulse width changes, thus maintaining signal synchronization stability while allowing clocking flexibility.
Data Source
AI summary
Disclosed is a data output controller that includes an enable signal controller, which generates a control signal having a predetermined pulse width in response to a DQ off signal and a write signal and generates a clock enable signal in response to a read signal and the control signal in synchronization with the control signal when the read signal is activated, and a clock generator that receives the enable signal and an internal clock signal and generates a data clock signal in synchronization with the internal clock signal during an activation period of the enable signal.