DRAM Output Driver Slew Rate Calibration for PVT Variations
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Solution Overview
Problem
Semiconductor device manufacturing faces challenges due to variations in process, voltage, and temperature (PVT) conditions, leading to inconsistent device performance and increased costs from wafer-to-wafer and die-to-die variations, which can result in devices operating outside design specifications, necessitating additional production to account for losses.
Innovation Solution
A slew rate control circuit is implemented, comprising a voltage regulation circuit and a calibrator that adjusts the drive strength of pre-drivers through a feedback loop, using a network of transistors and resistors to compensate for PVT variations, ensuring consistent output signal integrity by monitoring and adjusting channel conduction strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If different device geometries and fabrication facilities are used to meet market demand, then productivity increases, but manufacturing precision deteriorates due to wafer-to-wafer and die-to-die variations
Solution Approach 1:
The patent adjusts transistor gate channel width as a geometric parameter to compensate for PVT variations. By varying the gate channel width of pre-driver transistors, the circuit adapts to different process conditions, voltage levels, and temperatures, thereby maintaining consistent output slew rate across multiple fabrication facilities and process variations
Solution Approach 2:
The patent implements a feedback mechanism where the output signal is monitored and used to adjust the drive strength of pre-drivers. This feedback loop compensates for variations in real-time, ensuring that output signal integrity is maintained despite wafer-to-wafer and die-to-die variations that occur when scaling production across multiple facilities
2Productivity
If process variations are increased to meet demand, then productivity increases, but reliability deteriorates as devices operate outside design specifications
Solution Approach 1:
The patent introduces dynamic adjustment capabilities to the pre-driver circuitry, allowing the gate channel width to be adjusted based on actual operating conditions. This dynamic adaptation enables the circuit to maintain specification compliance even when process variations cause initial deviations, thereby ensuring reliability while allowing higher production volumes
Solution Approach 2:
By changing the geometric parameters of transistors (gate channel width) in response to process variations, the patent compensates for deviations from design specifications. This parameter adjustment mechanism ensures that devices remain reliable and compliant even when produced in high volumes across varying process conditions
3Manufacturing precision
If iterative tuning is performed to compensate for PVT variations, then manufacturing precision improves, but loss of time increases due to additional fabrication cycles
Solution Approach 1:
The patent performs preliminary adjustment of transistor gate channel widths during the initial fabrication process, incorporating compensation structures directly into the manufacturing flow. This preliminary action eliminates the need for subsequent iterative tuning cycles, achieving high manufacturing precision without additional time loss
Solution Approach 2:
The circuit incorporates self-adjusting mechanisms where the pre-driver automatically compensates for PVT variations through its internal feedback and adjustable geometry. This self-service capability eliminates the need for external iterative tuning processes, maintaining high precision while avoiding additional fabrication time
Data Source
AI summary
This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver circuit such as a DRAM output driver on a die. A selectable combination of series coupled transistors are configured as a parallel array of complementary inverter pairs to provide a divided voltage to a calibrator. The calibrator is configured to respond to a differential voltage to adjust the divided voltage such that the differential voltage is forced to zero. The calibrator outputs a plurality of discrete signals from an up/down counter to switch on and off the individual transistors of the parallel array to increase and decrease a collective current. In some embodiments, transistor channel currents are modulated to step-adjust a voltage based on a ratio associated with a static resistance. In various embodiments, the divided voltage is an analog voltage based on a resistance associated with trim circuitry.