Asymmetric DRAM Pad Array Layout for Pad-Plug Alignment
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Solution Overview
Problem
Current DRAM cells with recessed gate structures face structural defects due to high integration density, affecting performance and reliability.
Innovation Solution
A semiconductor structure with asymmetrically arranged peripheral pads of varying lengths at the SN pad array, featuring an asymmetric layout to maintain optimal contact areas with plugs, reducing misalignment issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the density of DRAM cell is continuously increased to meet high integration requirements, then the integration density is improved, but structural defects occur on the semiconductor structure
Solution Approach 1:
The patent applies asymmetry by arranging peripheral pads of different lengths at opposite sides of the pad array. Specifically, first peripheral pads have a first length and second peripheral pads have a second length different from the first length. This asymmetric configuration prevents structural defects that occur with symmetric arrangements when density is increased, while still achieving high integration density.
Solution Approach 2:
The patent implements local quality by making different peripheral pads have different lengths based on their positions. First peripheral pads at one side have a first length optimized for that side's requirements, while second peripheral pads at the opposite side have a second length optimized for their requirements. This localized optimization allows high density overall while preventing structural defects in specific regions.
2Ease of manufacture
If peripheral pads are arranged symmetrically, then the layout is simple and manufacturing is easier, but misalignment issues occur affecting contact reliability
Solution Approach 1:
The patent resolves the alignment issue by transitioning from symmetric pad arrangement to asymmetric arrangement. Peripheral pads at opposite sides have different lengths (first length vs. second length), which compensates for systematic alignment errors that occur during manufacturing. This asymmetric design maintains manufacturing simplicity while significantly improving pad-plug contact reliability.
3Device complexity
If all peripheral pads have the same length, then the structure is uniform and manufacturing is simplified, but contact area optimization is compromised
Solution Approach 1:
The patent optimizes contact area by applying local quality - different peripheral pads have different lengths tailored to their specific positions and requirements. First peripheral pads have a first length optimized for their location, while second peripheral pads have a second length optimized for theirs. This eliminates the need for uniform structure while maximizing overall contact reliability.
Data Source
AI summary
The present disclosure provides a semiconductor structure and a fabricating method thereof, including a pad array. The pad array includes a plurality of first pads, a first marginal pad, a second marginal pad, a plurality of second pads, and a plurality of third pads. The first pads are separately disposed. The first marginal pad is disposed at one side of the pad array, and includes a plurality of first branch pads. The second marginal pad is disposed at another side of the pad array being opposite to the first marginal pad, and includes a plurality of second branch pads. The second pads are separately disposed between the first branch pads. The third pads are separately disposed between the second branch pads, wherein a length of the second pads is smaller than a length of the third pads.