DRAM Partial Writing Method Reducing Power Consumption
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Solution Overview
Problem
Semiconductor memory devices consume high power during memory writing operations due to voltage swings on internal input/output lines, leading to increased power consumption compared to reading operations.
Innovation Solution
Implementing a partial writing method in semiconductor memory that utilizes a write amplifier circuit and address pins to selectively activate only a portion of internal input/output lines for data transmission based on column and row address instructions and operation codes, allowing for a partial writing mode that reduces power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full voltage swing is used on internal input/output lines during memory writing operation, then data transmission reliability is improved, but power consumption increases significantly
Solution Approach 1:
The patent applies partial action by selectively activating only a subset of internal input/output lines based on the column address. Instead of swinging all N lines during writing operations, only the required portion (determined by column address decoding) is activated, thereby reducing power consumption while maintaining reliable data transmission for the specific memory columns being written to
2Productivity
If all internal input/output lines are activated during memory writing, then writing speed is improved, but power consumption becomes two or three times higher than reading operation
Solution Approach 1:
The patent segments the internal input/output lines into multiple groups based on column address decoding. The writing operation is divided into smaller units where only the specific line segments corresponding to the target column are activated. This segmentation allows the memory to maintain high writing speed for the required columns while avoiding unnecessary power consumption on inactive line segments
3Use of energy by moving object
If voltage swing is reduced on internal input/output lines, then power consumption is reduced, but data transmission reliability may deteriorate
Solution Approach 1:
The patent applies local quality by maintaining full voltage swing amplitude only on the specific internal input/output lines that are currently active for the given column address. The voltage characteristics are localized to the active lines while inactive lines remain at zero swing, thus achieving power reduction without compromising the reliability of the actual data transmission paths
Data Source
AI summary
A semiconductor memory and a partial writing method are provided. The semiconductor memory includes a memory bank, a write amplifier circuit, a plurality of input/output pins and a plurality of address pins. The write amplifier circuit is coupled to the memory bank through a plurality of internal input/output lines. The plurality of input/output pins are coupled to the write amplifier circuit through a plurality of input lines. A part of plurality of address pins receive a column address instruction, and at least one of another part of the plurality of address pins receive an operation code. The semiconductor memory determines a part of the internal input/output lines for transmitting input data according to the operation code, and operates the write amplifier circuit to perform a partial writing mode according to the operation code so as to write the input data into the memory bank according to the column address instruction.