DRAM Peripheral Circuit Voltage Scaling for Standby Power Reduction
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Solution Overview
Problem
Dynamic Random Access Memory (DRAM) devices face challenges in minimizing power drain and latency, particularly during standby modes where data refresh is continuous, leading to increased power consumption and reduced battery life in portable devices.
Innovation Solution
The implementation of a semiconductor device with a superlattice structure and power switching devices that adjust voltage supply based on operating modes, allowing for reduced power consumption during standby modes by operating at lower voltages while maintaining current clock rates, and optimizing high and low voltage devices for minimal leakage and enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DRAM devices operate in standby mode with continuous data refresh, then data integrity is maintained, but power consumption increases
Solution Approach 1:
The patent implements dynamic voltage scaling by switching between first and second voltage supplies based on operational mode. During standby mode, the second voltage supply (lower voltage) is applied to peripheral circuits while the first voltage supply (higher voltage) maintains bit cell operation, dynamically adapting power consumption to actual operational needs while preserving data integrity through selective voltage application.
Solution Approach 2:
The patent applies different voltage levels to different parts of the DRAM device based on functional requirements. Peripheral circuits receive reduced voltage during standby mode while bit cells maintain higher voltage for data retention, creating localized quality differences that optimize both power consumption and data integrity across different functional regions of the device.
2Speed
If peripheral circuits operate at high voltage during active mode, then performance and speed are improved, but power consumption increases
Solution Approach 1:
The patent employs dynamic voltage scaling that adjusts the voltage supply to peripheral circuits based on the operational mode. During active mode, the first voltage supply provides higher voltage for maximum performance and speed. During standby mode, the second voltage supply reduces voltage to minimize power consumption, creating a dynamic adaptation between speed and energy usage requirements.
Solution Approach 2:
The patent changes the voltage parameter of peripheral circuits based on operational mode. By switching between two discrete voltage levels (first voltage supply for active mode, second voltage supply for standby mode), the system optimizes the balance between operational speed and power consumption, adjusting the electrical parameter to match functional requirements.
Data Source
AI summary
A semiconductor device may include a plurality of memory cells, and at least one peripheral circuit coupled to the plurality of memory cells and comprising a superlattice. The superlattice may include a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a first power switching device configured to couple the at least one peripheral circuit to a first voltage supply during a first operating mode, and a second power switching device configured to couple the at least one peripheral circuit to a second voltage supply lower than the first voltage supply during a second operating mode.