Semiconductor Pillar Contact Layout for DRAM Alignment Accuracy
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Solution Overview
Problem
The existing 4F2 storage architecture in DRAMs faces challenges with alignment difficulty and low alignment accuracy due to the small area of the storage node contact structure.
Innovation Solution
A semiconductor structure and manufacturing method that includes forming main semiconductor pillars with sub-pillars and isolation layers, etching a sacrificial pattern to expose the sub-pillars, forming a conductive contact layer, patterning it into independent structures, and filling an isolation material to form additional layers, thereby reducing process difficulty and improving alignment accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the storage node contact structure area is reduced to achieve higher integration density, then the integration density is improved, but the alignment difficulty increases and alignment accuracy decreases
Solution Approach 1:
The main semiconductor pillar is divided into first and second sub-semiconductor pillars spaced apart from each other. This segmentation allows the conductive contact layer to be formed between them, creating a larger effective contact area while maintaining compact overall structure, thereby resolving the contradiction between integration density and alignment accuracy.
Solution Approach 2:
The conductive contact layer is formed extending along the second direction (horizontal dimension) between the sub-pillars, rather than only vertically. This dimensional extension increases the contact area without significantly increasing the footprint area, thus improving alignment accuracy while maintaining integration density.
2Productivity
If the storage node contact structure area is reduced to achieve higher integration density, then the integration density is improved, but the process complexity increases
Solution Approach 1:
The formation of conductive contact structures is merged with the formation of isolation layers. The conductive contact layer is formed between the sub-pillars during the same process sequence as the isolation layer deposition, eliminating the need for separate conductive contact hole formation processes and reducing overall process complexity.
Solution Approach 2:
The conductive contact layer serves multiple functions: it provides electrical contact between bit lines and word lines, acts as part of the isolation structure, and enables the 4F2 storage architecture. This multi-functionality reduces the number of dedicated process steps needed, thereby reducing process complexity while maintaining high integration density.
3Reliability
If the contact area between conductive structures and semiconductor pillars is increased to reduce contact resistance, then the contact resistance is reduced, but the area occupied by contact structures increases
Solution Approach 1:
The conductive contact layer is strategically positioned only between the first and second sub-semiconductor pillars where electrical contact is needed, rather than covering the entire surface. This localized approach increases contact area where necessary to reduce contact resistance while minimizing the overall area occupied by contact structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution eliminates the need for forming separate conductive contact holes, reduces process complexity, and increases the contact area between conductive structures and semiconductor pillars, thereby lowering contact resistance and improving reliability.
Implementation Method 1
an etching rate of an etching material on the first sacrificial pattern is greater than an etching rate of the etching material on the first isolation layer and the second isolation layer
Data Source
AI summary
A method for manufacturing a semiconductor structure includes: forming an initial structure, where the initial structure includes a plurality of main semiconductor pillars, each of the main semiconductor pillars includes a first sub-semiconductor pillar and a second sub-semiconductor pillar, a first sacrificial pattern is provided on the first sub-semiconductor pillar and the second sub-semiconductor pillar; etching the first sacrificial pattern to expose the first sub-semiconductor pillar and the second sub-semiconductor pillar; forming a conductive contact layer; patterning the conductive contact layer to form a plurality of conductive contact structures, where each of the conductive contact structures is in contact with the first sub-semiconductor pillar or the second sub-semiconductor pillar; and filling an isolation material in a gap between the conductive contact structures to form a third isolation layer.