DRAM-PIM Filtering Architecture for OLAP Memory Bottlenecks
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Solution Overview
Problem
OLAP systems face memory bottlenecks due to the disparity between memory density growth and bus speed improvements, leading to inefficiencies in data transfer and query performance, particularly in memory-bound filtering operations.
Innovation Solution
Implementing a DRAM-PIM filtering architecture with bank-level and sub-array-level filtering units (BFU and SFU) that perform filtering operations directly within the memory hierarchy, reducing data movement and alleviating bottlenecks by leveraging DRAM's inherent parallelism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If data is stored in traditional memory architecture with columnar layout, then spatial locality is enhanced, but memory bottleneck occurs due to disparity between memory density growth and bus speed improvements
Solution Approach 1:
The patent introduces a new dimension of processing by implementing filtering units within the memory hierarchy itself, transforming the traditional von Neumann architecture into a more integrated structure where filtering operations occur at multiple levels (bank-level and sub-array-level) within the DRAM chip, eliminating the need to transfer all data through external buses
Solution Approach 2:
The patent introduces filtering units as intermediary components between the data storage sub-arrays and the external memory interface. These filtering units act as mediators that selectively pass data based on filtering predicates, preventing unnecessary data from being transferred through the memory bus to the processor
2Ease of operation
If all data is transferred from memory to processor for filtering operations, then complete data access is achieved, but data movement increases causing memory bottleneck
Solution Approach 1:
The patent extracts the filtering function from the processor and places it directly within the memory hierarchy at multiple levels. This extraction allows filtering operations to be performed on data while it resides in memory, eliminating the need to transfer all data to the processor and reducing overall data movement
Solution Approach 2:
The patent performs filtering operations preliminarily within the memory hierarchy before data is transferred to the processor. By applying filtering predicates at bank-level and sub-array-level filtering units, the system pre-processes data in memory, ensuring that only relevant data needs to be moved to the processor for subsequent operations
3Adaptability or versatility
If filtering operations are performed at processor level, then centralized control is maintained, but query performance decreases due to memory-bound operations
Solution Approach 1:
The patent segments the filtering functionality into multiple distributed filtering units within the memory hierarchy, including bank-level filtering units (BFUs) and sub-array-level filtering units (SFUs). Each filtering unit operates independently on its associated data sub-array, enabling parallel processing while maintaining centralized control through coordinated operation
Solution Approach 2:
The patent merges the filtering function with the memory structure by integrating filtering units directly into the DRAM chip architecture. This merging combines storage and processing capabilities at multiple levels, allowing filtering operations to occur where data resides without requiring separate data movement cycles
Data Source
AI summary
A bank-level dynamic random access memory (DRAM) process-in-memory (DRAM-PIM) filtering architecture is provided to accelerate database online analytical processing (OLAP) queries. Also, sub-array-level dynamic random access memory (DRAM) process-in-memory (DRAM-PIM) filtering architectures are provided to accelerate database online analytical processing (OLAP) queries.