DRAM Power Interrupt Protection Logic
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Solution Overview
Problem
Dynamic random-access memory (DRAM) devices in automotive applications are vulnerable to unauthorized access when removed from their circuit boards and transferred to another socket, as they can lose power temporarily, allowing malicious users to access stored data.
Innovation Solution
Incorporating protection logic within the memory device that monitors CMOS voltage and executes operations such as pre-charging, pausing self-refresh mode, forcing a reset, or rewriting data upon detecting a power interrupt, using a combination of pre-charge logic, refresh disable logic, reset logic, and re-write logic to secure data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If DRAM is placed in self-refresh or standby mode to conserve energy, then energy consumption is reduced, but the device becomes vulnerable to unauthorized access when removed from its circuit board
Solution Approach 1:
The patent implements preliminary action by detecting power interrupt conditions before unauthorized access can occur. When a power interrupt is detected (indicating the DRAM may be removed from its board), the system proactively executes protective operations such as pre-charging memory banks, pausing self-refresh mode, forcing reset, or rewriting data before the malicious user can access the data. This anticipatory measure resolves the contradiction by maintaining security without requiring the DRAM to remain in high-power operational mode.
Solution Approach 2:
The patent converts the harmful power interrupt condition (which enables unauthorized access) into a beneficial trigger for protective actions. Instead of merely reacting to power loss, the system uses the power interrupt detection as a signal to execute security operations that prevent data exposure. The power interrupt, which would normally be a security vulnerability, becomes the activation condition for the protection mechanism, thereby converting the harm into a benefit.
2Reliability
If protection logic is added to monitor CMOS voltage and execute protective operations, then data security is improved, but device complexity increases
Solution Approach 1:
The protection logic is designed with multi-functionality to reduce overall device complexity. The same protection logic circuit that detects power interrupt conditions also controls multiple different protective operations (pre-charge, pause self-refresh, force reset, rewrite data). Rather than implementing separate dedicated circuits for each protective function, a single universal protection logic module handles all security-related tasks, thereby improving data security without proportionally increasing device complexity.
Solution Approach 2:
The patent merges the protection logic functionality into the existing DRAM control structure. The protection logic is integrated with the memory controller and works cooperatively with existing DRAM operational modes (self-refresh, pre-charge, reset). By combining the new security functionality with existing control mechanisms rather than adding entirely separate systems, the patent achieves enhanced data security while minimizing the increase in device complexity.
Data Source
AI summary
The disclosed embodiments describe methods, devices, and computer-readable media for protecting the integrity of volatile memory devices. In one embodiment, a method is disclosed comprising detecting a power interrupt condition of a memory device; and executing at least one operation in response to detecting the power interrupt condition, the operation selected from the group of operations consisting of: placing the memory device in a pre-charge mode, pausing a self-refresh mode of the memory device, forcing the memory device into a reset mode, or rewriting data in the memory device.