DRAM Bank Power-State Control Without Waveform Degradation
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Solution Overview
Problem
Existing electronic devices face challenges in reducing power consumption during power saving mode without degrading waveform quality when transitioning from normal mode, particularly due to the need to divide the power supply layer, which can disrupt current flow and deteriorate signal transmission.
Innovation Solution
The implementation of a transition processing portion that manages the state transitions of DRAMs between different power consumption states, including storing return data and transitioning DRAMs to lower power states without dividing the power supply layer, thereby maintaining waveform quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If data is saved from first DRAM to second DRAM and power supply to first DRAM is stopped, then power consumption is reduced, but waveform quality deteriorates due to power supply layer division
Solution Approach 1:
The invention divides the DRAM array into multiple banks (first DRAM and second DRAM) that can operate independently. During power saving mode, only the necessary DRAM bank maintains active state while others transition to lower power states, reducing overall power consumption without requiring division of the power supply layer itself. This segmentation allows selective power management at the DRAM bank level rather than requiring physical power supply layer segmentation.
Solution Approach 2:
The invention changes the operational parameters of DRAMs by introducing multiple power consumption states (first state with full power, second state with reduced power, third state with minimal power). By dynamically transitioning DRAMs between these states based on operational needs, the system reduces power consumption during power saving mode while maintaining waveform quality through controlled parameter changes rather than physical structural changes to the power supply layer.
2Use of energy by stationary object
If DRAMs transition to low power state, then power consumption is reduced, but data holding capability is lost
Solution Approach 1:
Before transitioning DRAMs to low power states, the invention performs preliminary actions by saving necessary data to persistent storage or maintaining critical data in actively powered DRAM banks. This preliminary data preservation ensures that when DRAMs transition to second or third states with reduced power consumption, the essential information is already secured and can be quickly restored when power is replenished, preventing data loss while enabling power savings.
Solution Approach 2:
The invention introduces an intermediary mechanism (such as a buffer memory or cache system) that temporarily holds data during transitions between active and low-power states. This intermediary allows DRAMs to transition to power-saving states without directly losing data, as the intermediary maintains the data bridge between the DRAM and persistent storage, enabling smooth state transitions while preserving information.
Data Source
AI summary
An electronic device includes a substrate, a plurality of DRAMs, and a transition processing portion. The substrate includes a power supply layer adjacent to a wiring layer. The plurality of DRAMs are capable of transitioning from a first state in which data can be held to a second state in which data cannot be held and that consumes less power than the first state, and receive power from the power supply layer. The transition processing portion, in a case where an operating mode of the electronic device moves from a normal mode to power saving mode that consumes less power than the normal mode, stores return data used when returning to the normal mode in part of the plurality of DRAMs, and causes each of the DRAMs in which the return data is not stored to transition from the first state to the second state.