DRAM Control Circuit for Power-Down Exit Signal Decoding
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Solution Overview
Problem
Dynamic random access memory (DRAM) systems face challenges in decoding command/address signals during power down mode, particularly when command/address inversion is present, which prevents normal operation and exit from the power down mode.
Innovation Solution
A control circuit comprising a flag signal generation circuit, an input processing circuit, and a logic decoding circuit, which processes command/address control signals and initial inversion flags to generate command/address inversion flags and intermediate command/address signals, enabling proper decoding of power down mode entry and exit signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If command/address inversion is applied to reduce power consumption in power down mode, then power saving is improved, but decoding of power down mode exit signals fails
Solution Approach 1:
The patent introduces an intermediary inversion flag signal that mediates between the command/address inversion mechanism and the power down mode exit signal. This flag signal acts as a translator that converts the inverted command/address signals back to their original form for proper decoding of the exit signal, while still allowing power consumption reduction when in power down mode.
Solution Approach 2:
The system dynamically adjusts the inversion state based on the power down mode status. When in power down mode, command/address signals are inverted to reduce power consumption. When exiting power down mode, the inversion state is dynamically changed to allow proper decoding of the exit signal, achieving adaptability between power saving and reliable operation.
2Loss of energy
If command/address signals are inverted during power down mode, then power consumption is reduced, but the system cannot normally exit power down mode
Solution Approach 1:
The inversion flag signal serves as an intermediary that tracks the inversion state and enables proper interpretation of command/address signals during mode transitions. This mediator allows the system to maintain inverted signals for power saving while still being able to correctly identify and respond to power down mode exit signals.
Solution Approach 2:
The system performs preliminary action by setting the inversion flag signal before entering power down mode. This preliminary configuration ensures that when the system needs to exit power down mode, the inversion state is already properly configured to allow correct decoding of the exit signal without requiring complex real-time adjustments.
Data Source
AI summary
Provided are a control circuit, a control method, and a memory. The control circuit includes: a flag signal generation circuit, configured to generate a command/address inversion flag signal based on a command/address control signal and an initial inversion flag signal; an input processing circuit, configured to generate a first intermediate command/address signal based on the command/address control signal and an initial command/address signal; and a logic decoding circuit, configured to: receive the first intermediate command/address signal and the command/address inversion flag signal, and generate a power down mode entry signal or a power down mode exit signal based on the command/address inversion flag signal and the first intermediate command/address signal.