DRAM PRAC Error Alerting for Immediate Row Hammer Mitigation
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Solution Overview
Problem
Existing DRAM systems face challenges in accurately detecting and immediately notifying the host of Per Row Activation Counting (PRAC) counter errors, which are prone to errors themselves, leading to delayed mitigation of row hammer attacks and potential data corruption.
Innovation Solution
Implement a system and method for immediately notifying the host of a PRAC counter error through an alert signal logic block, storing the affected row's address in mode registers, and enabling real-time polling to enable prompt error handling and mitigation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PRAC counter errors are detected using conventional methods, then error detection capability is provided, but notification delay occurs and immediate mitigation cannot be achieved
Solution Approach 1:
The patent implements preliminary action by pre-configuring the alert signal logic block and mode registers before errors occur. When a PRAC counter error is detected, the system immediately stores the affected row address in the mode registers and generates an alert signal without delay, enabling the host to take corrective action promptly. This preliminary preparation of error handling infrastructure eliminates notification delays.
Solution Approach 2:
The patent establishes a feedback mechanism where the DRAM continuously monitors PRAC counter values and provides immediate feedback to the host through alert signals. The mode registers store error information that can be read by the host, creating a closed-loop feedback system that enables real-time error notification and immediate mitigation of row hammer attacks.
2Device complexity
If PRAC counter errors are not immediately notified, then system complexity is reduced, but row hammer attacks can proceed unchecked causing data corruption
Solution Approach 1:
The patent extracts the critical error notification function from the complex PRAC error handling system. By using dedicated alert signal logic blocks and mode registers, the system separates the essential error alerting mechanism from the broader error correction infrastructure, enabling immediate notification with minimal added complexity while effectively countering row hammer attacks.
3Ease of manufacture
If conventional error notification methods are used, then implementation is simpler, but timely corrective action by host cannot be taken
Solution Approach 1:
The patent introduces mode registers as an intermediary mechanism between the PRAC counter error detection and the host's corrective action. The mode registers store error information in a readily accessible format, serving as a bridge that enables the host to quickly read error details and respond appropriately without complex communication protocols, thus maintaining implementation simplicity while achieving timely corrective action.
Data Source
AI summary
Implementations herein describe a system including a system-on-chip and a dynamic random-access memory (DRAM) in communication with the SoC, the DRAM including at least a per row activation counting (PRAC) counter, the system configured to detect an error in the PRAC counter, transmit a signal to an alert signal logic block in the DRAM once the error in the PRAC counter has been detected, and allow the alert signal logic block to provide the signal to the SoC once the alert signal logic block receives the signal.