DRAM Write Training With PRBS Checking for Concurrent Pin Testing
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Solution Overview
Problem
Existing DRAM write training techniques require lengthy data patterns that consume significant time and memory resources, and traditional methods necessitate storing and reading back these patterns, reducing available bandwidth and memory space.
Innovation Solution
Implementing a pseudorandom bit sequence (PRBS) pattern checker using linear feedback shift registers (LFSRs) to train all data interface pins concurrently, eliminating the need to store and read back lengthy patterns, and instead providing a pass/fail result to determine training success.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If lengthy data patterns are used for write training, then training reliability is improved, but training time and memory resources are consumed
Solution Approach 1:
The patent extracts the data pattern storage function from the DRAM memory core and places it in a separate FIFO buffer. This allows the training data to be stored externally rather than consuming DRAM capacity, and enables the training process to read patterns from the buffer without writing them back to memory, thereby reducing training time while maintaining reliability
Solution Approach 2:
The patent introduces a FIFO buffer as an intermediary between the memory controller and the DRAM memory core. This buffer temporarily stores the training data patterns, allowing the controller to load patterns once and reuse them for multiple training iterations without repeatedly writing to and reading from the DRAM, thus reducing overall training time
2Reliability
If lengthy data patterns are stored in DRAM for training, then training accuracy is improved, but available memory space is reduced
Solution Approach 1:
The patent extracts the training data storage function from the DRAM memory core by using a separate FIFO buffer. This separation allows the DRAM to maintain its full capacity for actual data storage operations while the FIFO buffer handles the training pattern storage, eliminating the trade-off between training accuracy and available memory space
Solution Approach 2:
The patent uses a FIFO buffer to create a copy of the training data patterns externally. Instead of storing patterns directly in DRAM, the system loads the same patterns into the FIFO buffer multiple times for training iterations, eliminating the need to consume DRAM capacity for training data
3Reliability
If traditional write training methods are used, then training completeness is ensured, but bandwidth is reduced due to repeated read/write operations
Solution Approach 1:
The patent performs preliminary action by loading the training data patterns into the FIFO buffer before the actual training begins. The controller loads the patterns once into the buffer, then reuses these pre-loaded patterns for multiple training iterations, eliminating the need to repeatedly write patterns to DRAM during training and thus maintaining bandwidth for actual data operations
Solution Approach 2:
The FIFO buffer acts as an intermediary that decouples the training process from the DRAM write operations. By storing patterns in the buffer beforehand, the system can perform training without repeatedly accessing DRAM for pattern loading, thereby preserving bandwidth for actual data transfer operations
Data Source
AI summary
Various embodiments include a memory device that is capable of performing write training operations. Prior approaches for write training involve storing a long data pattern into the memory followed by reading the long data pattern to determine whether the data was written to memory correctly. Instead, the disclosed memory device stores a first data pattern (e.g., in a FIFO memory within the memory device) or generates the first data pattern (e.g., using PRBS) that is compared with a second data pattern being transmitted to the memory device by an external memory controller. If data patterns match, then the memory device stores a pass status in a register, otherwise a fail status is stored in the register. The memory controller reads the register to determine whether the write training passed or failed.