DRAM Memory Controller Preprocessor for Deep Queue Timing Closure
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing DRAM controller architectures face challenges in achieving high performance targets due to RTL timing closure issues with deep reordering scheduler queues, particularly at 1 GHz operation, which limits the achievable bandwidth and efficiency.
Innovation Solution
A novel DRAM controller architecture is introduced, partitioning the controller into a reordering preprocessor and scheduler, with a shorter reordering scheduler queue and a separate reordering preprocessor that operates independently, allowing easier timing closure and higher performance through optimized transaction reordering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the reordering scheduler queue depth is increased to improve DRAM performance, then the achievable bandwidth and efficiency increase, but the RTL timing closure becomes more difficult to achieve
Solution Approach 1:
The patent divides the traditional monolithic reordering scheduler into two separate components: a reordering preprocessor and a reordering scheduler. The preprocessor handles initial transaction reordering and filtering, while the scheduler manages the deep queue and final scheduling decisions. This segmentation allows the scheduler queue to achieve deeper depth (128 entries) without proportionally increasing the complexity of timing closure, as the preprocessing work is distributed to the separate preprocessor unit.
2Productivity
If the queue depth is increased to achieve higher DRAM performance targets, then the bandwidth increases, but the operating speed becomes harder to maintain at 1 GHz
Solution Approach 1:
The reordering preprocessor performs preliminary reordering and filtering of transactions before they enter the deep reordering scheduler queue. By pre-processing transactions and organizing them in advance, the system can maintain 1 GHz operating speed even with a 128-entry deep queue, as the critical path timing is reduced and the scheduler receives pre-organized transaction streams.
Data Source
AI summary
A state-of-the-art memory controller and methods for using the same are disclosed. The memory controller is intended for use with dynamic random-access memory (DRAM) circuitry. In one example, a memory controller includes a reordering preprocessor circuitry coupled to a reordering scheduler circuitry. The reordering scheduler circuitry is configured to control a reordering scheduler queue, and is coupled to DRAM circuitry. The reordering preprocessor circuitry is configured to control a preprocessor queue and reorder transactions in the preprocessor queue so as to increase the DRAM circuitry performance.