Protruding-Channel DRAM Peripheral Transistors for Stronger Gate Coupling
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Solution Overview
Problem
The performance of dynamic random access memory (DRAM) is limited by the transistors in peripheral circuits, which have not evolved significantly despite advancements in memory cell transistors, making them the weak link in improving DRAM performance.
Innovation Solution
The implementation of a memory device with a peripheral circuit featuring three-dimensional transistors having protruding channel structures and gate structures, where the protruding channel structures have a bottom part and an upper part with a top width smaller than the bottom width, enhancing gate coupling area without increasing dimension, and including a work function layer for further adjustment in P-type transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If three-dimensional transistors with protruding channel structures are implemented in peripheral circuits, then transistor performance is enhanced, but device complexity increases
Solution Approach 1:
The patent applies dimensionality change by transitioning from planar transistors to three-dimensional transistors with protruding channel structures. The channel structure extends vertically out of the substrate plane, creating a three-dimensional configuration that increases gate coupling area and improves transistor performance while maintaining a compact footprint.
Solution Approach 2:
The gate structure is designed to cover and envelop the protruding channel structure, creating a nested configuration where the gate surrounds the channel from multiple directions. This nesting approach maximizes the gate-channel overlap area, enhancing transistor performance without proportionally increasing the overall device area.
2Reliability
If the upper part of the protruding channel structure has a tapered shape with smaller top width, then gate coupling area is increased, but manufacturing precision requirements increase
Solution Approach 1:
The channel structure employs parameter changes in its geometry, specifically a tapered shape where the top width is smaller than the bottom width. This gradual width reduction creates a funnel-like structure that concentrates the channel under the gate, increasing the effective gate coupling area. The parameter change is designed to be manufacturable while achieving the desired performance enhancement.
Data Source
AI summary
A method for forming a memory device includes: forming an array of memory cells, wherein the memory cells respectively include an access transistor embedded in a semiconductor substrate and a storage capacitor over the semiconductor substrate and coupled to the access transistor; and forming a peripheral circuit around the memory cells, wherein the peripheral circuit includes a first transistor and a second transistor on the semiconductor substrate and each including a protruding channel structure and a gate structure covering the protruding channel structure, the protruding channel structure has a bottom part and an upper part, and the upper part has a top width and a bottom width smaller the top width